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1980 IEEE International Solid-State Circuits Conference. Digest of Technical Papers最新文献

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Analog signal processing: Digital or linear VLSI? 模拟信号处理:数字还是线性VLSI?
1980 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI: 10.1109/ISSCC.1980.1156142
G. Baldwin, R. Blauschild
{"title":"Analog signal processing: Digital or linear VLSI?","authors":"G. Baldwin, R. Blauschild","doi":"10.1109/ISSCC.1980.1156142","DOIUrl":"https://doi.org/10.1109/ISSCC.1980.1156142","url":null,"abstract":"AS logic technologies are scaled down, traditional analog functions such as filtering, tone generation and mixing may be done with large digital processors surrounded by D/A converters. The same technological advances have also made feasible complex multi-amplifier systems in which signals remain in the analog domain. The panel will discuss these two approaches with emphasis on cost/performance benefits based on present, as well as projected technological developments.","PeriodicalId":229101,"journal":{"name":"1980 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123232734","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
One Mb bubble memory with support electronics 带有支持电子器件的1mb气泡存储器
1980 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI: 10.1109/ISSCC.1980.1156141
S. Nicolino
{"title":"One Mb bubble memory with support electronics","authors":"S. Nicolino","doi":"10.1109/ISSCC.1980.1156141","DOIUrl":"https://doi.org/10.1109/ISSCC.1980.1156141","url":null,"abstract":"A 1Mb bubble memory system, including the bubble device, made on garnet material, and five silicon support devices, made with bipolar, CMOS, VMOS, NMOS and HMOS processes, will be discussed.","PeriodicalId":229101,"journal":{"name":"1980 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"XXIII 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131063944","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 500V monolithic bidirectional 2×2 crosspoint array 500V单片双向2×2交叉点阵列
1980 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI: 10.1109/ISSCC.1980.1156120
P. Shackle, A. Hartman, T. Riley, J. North, J. Berthold, J. Davis
{"title":"A 500V monolithic bidirectional 2×2 crosspoint array","authors":"P. Shackle, A. Hartman, T. Riley, J. North, J. Berthold, J. Davis","doi":"10.1109/ISSCC.1980.1156120","DOIUrl":"https://doi.org/10.1109/ISSCC.1980.1156120","url":null,"abstract":"This paper will report on a high voltage IC employing a gated diode switch replacing metallic switches normally used for the concentrator function that meets the telephone loop switch requirements, which are voltage blocking to +500V, surge conduction to 1A levels and interruption of direct currents forced by the 48V dc normally used to power telephone loops.","PeriodicalId":229101,"journal":{"name":"1980 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"72 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133132007","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Solid-state image sensors for low-cost TV cameras 用于低成本电视摄像机的固态图像传感器
1980 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI: 10.1109/ISSCC.1980.1156024
M. Ishikawa, W. Kosonocky
{"title":"Solid-state image sensors for low-cost TV cameras","authors":"M. Ishikawa, W. Kosonocky","doi":"10.1109/ISSCC.1980.1156024","DOIUrl":"https://doi.org/10.1109/ISSCC.1980.1156024","url":null,"abstract":"Currently, there is a growing interest in the development of low-cost solid-state color TV cameras. Design approaches and tradeoffs for the key element - solid-state image sensors-will be assessed. Topics will include performance, advances in the IC processing technology leading to the fabrication of the sensors with a satisfactory cosmetic quality and at reasonable cost, and the advantages of different types of color-filter techniques.","PeriodicalId":229101,"journal":{"name":"1980 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"79 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134394596","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
An integrated realtime programmable transversal fiIter 一个集成的实时可编程横向滤波器
1980 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI: 10.1109/ISSCC.1980.1156128
Hsin-fu Tseng, Lyon Lin, S. Tanaka, Pao Chen
{"title":"An integrated realtime programmable transversal fiIter","authors":"Hsin-fu Tseng, Lyon Lin, S. Tanaka, Pao Chen","doi":"10.1109/ISSCC.1980.1156128","DOIUrl":"https://doi.org/10.1109/ISSCC.1980.1156128","url":null,"abstract":"A fully integrated 32-tap realtime programmable transversal filter will be described. Device uses RAMs and 16 MDACs for tap weight programming and pipe-organ BBD registers for signal delay and summing.","PeriodicalId":229101,"journal":{"name":"1980 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"259 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133627080","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Universal versus dedicated microprocessors 通用微处理器和专用微处理器
1980 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI: 10.1109/ISSCC.1980.1156101
P. Verhofstadt
{"title":"Universal versus dedicated microprocessors","authors":"P. Verhofstadt","doi":"10.1109/ISSCC.1980.1156101","DOIUrl":"https://doi.org/10.1109/ISSCC.1980.1156101","url":null,"abstract":"Although microprocessor CPUs are becoming increasingly powerful, it appears that raw speed and greater word length may not solve all of the microprocessor problems .... Particularly, the ominous software burden makes that direction increasingly less attractive .... One way of relieving that situation appears to be the development of a number of dedicated processors suited to a particular task or class of tasks .... However, that causes loss of universality ....The pros and cons of both approaches will be discussed.","PeriodicalId":229101,"journal":{"name":"1980 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"78 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122452170","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 200MHz PLL CMOS LSI with DSA E/D NMOS prescaler 带有DSA E/D NMOS预缩放器的200MHz锁相环CMOS LSI
1980 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI: 10.1109/ISSCC.1980.1156071
T. Uno, T. Saeki, Y. Nabeta, K. Fukui, T. Nezu
{"title":"A 200MHz PLL CMOS LSI with DSA E/D NMOS prescaler","authors":"T. Uno, T. Saeki, Y. Nabeta, K. Fukui, T. Nezu","doi":"10.1109/ISSCC.1980.1156071","DOIUrl":"https://doi.org/10.1109/ISSCC.1980.1156071","url":null,"abstract":"A 200MHz single-chip PLL using a DSA E/D NMOS-compatihie N-well CMOS concept will be presented. Approach is best suited to 4b microprocessors simplifying development of digital frequency synthesizers for tuning systems.","PeriodicalId":229101,"journal":{"name":"1980 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"70 5 PT.1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123253014","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Multi-level logic gate implementation in GaAs ICs using schottky diode-FET logic 利用肖特基二极管-场效应晶体管逻辑实现GaAs集成电路中的多级逻辑门
1980 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI: 10.1109/ISSCC.1980.1156064
R. Eden, F. Lee, S. Long, B. Welch, R. Zucca
{"title":"Multi-level logic gate implementation in GaAs ICs using schottky diode-FET logic","authors":"R. Eden, F. Lee, S. Long, B. Welch, R. Zucca","doi":"10.1109/ISSCC.1980.1156064","DOIUrl":"https://doi.org/10.1109/ISSCC.1980.1156064","url":null,"abstract":"An extension of the Schottky diode-FET logic circuit approach for ultra high-speed, low-power planar GaAs digital ICs to configurations allowing up to three levels of logic to be performed in one gate, will be reported.","PeriodicalId":229101,"journal":{"name":"1980 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123540800","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 13
A 5ns monolithic D/A subsystem 5ns单片D/A子系统
1980 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI: 10.1109/ISSCC.1980.1156051
P. Saul, P. Ward, A. Fryers
{"title":"A 5ns monolithic D/A subsystem","authors":"P. Saul, P. Ward, A. Fryers","doi":"10.1109/ISSCC.1980.1156051","DOIUrl":"https://doi.org/10.1109/ISSCC.1980.1156051","url":null,"abstract":"An 8b DAC with 5ns settling capability, a 1.3ns comparator and a reference with < 80ppm/°C stability, integrated on one chip, to provide all analog functions for 15MHz successive approximation A/D conversion, will be discussed.","PeriodicalId":229101,"journal":{"name":"1980 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131877153","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
A single 5V 64K dynamic RAM 单个5V 64K动态RAM
1980 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI: 10.1109/ISSCC.1980.1156076
K. Itoh, R. Hori, H. Masuda, Y. Kamigaki, H. Kawamoto, H. Katto
{"title":"A single 5V 64K dynamic RAM","authors":"K. Itoh, R. Hori, H. Masuda, Y. Kamigaki, H. Kawamoto, H. Katto","doi":"10.1109/ISSCC.1980.1156076","DOIUrl":"https://doi.org/10.1109/ISSCC.1980.1156076","url":null,"abstract":"This paper will report on a single 5V, 64K dynamic RAM with a substrate-bias generator, typical power dissipation of 170mW at 300ns cycle time, access time of 120ns and 25.8mm2chip area.","PeriodicalId":229101,"journal":{"name":"1980 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116908836","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 34
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