{"title":"利用肖特基二极管-场效应晶体管逻辑实现GaAs集成电路中的多级逻辑门","authors":"R. Eden, F. Lee, S. Long, B. Welch, R. Zucca","doi":"10.1109/ISSCC.1980.1156064","DOIUrl":null,"url":null,"abstract":"An extension of the Schottky diode-FET logic circuit approach for ultra high-speed, low-power planar GaAs digital ICs to configurations allowing up to three levels of logic to be performed in one gate, will be reported.","PeriodicalId":229101,"journal":{"name":"1980 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"12 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"13","resultStr":"{\"title\":\"Multi-level logic gate implementation in GaAs ICs using schottky diode-FET logic\",\"authors\":\"R. Eden, F. Lee, S. Long, B. Welch, R. Zucca\",\"doi\":\"10.1109/ISSCC.1980.1156064\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"An extension of the Schottky diode-FET logic circuit approach for ultra high-speed, low-power planar GaAs digital ICs to configurations allowing up to three levels of logic to be performed in one gate, will be reported.\",\"PeriodicalId\":229101,\"journal\":{\"name\":\"1980 IEEE International Solid-State Circuits Conference. Digest of Technical Papers\",\"volume\":\"12 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1900-01-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"13\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"1980 IEEE International Solid-State Circuits Conference. Digest of Technical Papers\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISSCC.1980.1156064\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"1980 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISSCC.1980.1156064","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Multi-level logic gate implementation in GaAs ICs using schottky diode-FET logic
An extension of the Schottky diode-FET logic circuit approach for ultra high-speed, low-power planar GaAs digital ICs to configurations allowing up to three levels of logic to be performed in one gate, will be reported.