5ns单片D/A子系统

1980 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI:10.1109/ISSCC.1980.1156051

P. Saul, P. Ward, A. Fryers

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引用次数: 4

摘要

将讨论一个具有5ns沉降能力的8b DAC，一个1.3ns比较器和一个稳定性< 80ppm/°C的参考，集成在一个芯片上，为15MHz连续近似a /D转换提供所有模拟功能。

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A 5ns monolithic D/A subsystem

An 8b DAC with 5ns settling capability, a 1.3ns comparator and a reference with < 80ppm/°C stability, integrated on one chip, to provide all analog functions for 15MHz successive approximation A/D conversion, will be discussed.

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来源期刊

1980 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

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