{"title":"A 200MHz PLL CMOS LSI with DSA E/D NMOS prescaler","authors":"T. Uno, T. Saeki, Y. Nabeta, K. Fukui, T. Nezu","doi":"10.1109/ISSCC.1980.1156071","DOIUrl":null,"url":null,"abstract":"A 200MHz single-chip PLL using a DSA E/D NMOS-compatihie N-well CMOS concept will be presented. Approach is best suited to 4b microprocessors simplifying development of digital frequency synthesizers for tuning systems.","PeriodicalId":229101,"journal":{"name":"1980 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"70 5 PT.1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"1980 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISSCC.1980.1156071","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
A 200MHz single-chip PLL using a DSA E/D NMOS-compatihie N-well CMOS concept will be presented. Approach is best suited to 4b microprocessors simplifying development of digital frequency synthesizers for tuning systems.