一种用于电信应用的数字信号处理器

1980 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI:10.1109/ISSCC.1980.1156117

J. Boddie, G. Daryanani, I. Eldumiati, R. Gadenz, J. Thompson, S. Walters, R. Pedersen

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引用次数: 21

摘要

本文将介绍一种可编程数字信号处理器芯片，该芯片可以按指令解码，提取数据，进行16 × 20b的乘法运算，并在80ns内将结果加到40b的累加器中。电路允许在一个芯片上实现双音多频接收机或低速调制解调器的所有信号处理功能。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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A digital signal processor for telecommunications applications

This paper will report on a programmable digital signal processor chip which can decode on instruction, fetch data, perform a 16 × 20b multiply, and add the resultant to a 40b accumulator in 80ns. Circuit permits all signal processing functions of a dual-tone multifrequency receiver or a low-speed modem to be realized on one chip.

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来源期刊

1980 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

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