J. Boddie, G. Daryanani, I. Eldumiati, R. Gadenz, J. Thompson, S. Walters, R. Pedersen
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引用次数: 21
Abstract
This paper will report on a programmable digital signal processor chip which can decode on instruction, fetch data, perform a 16 × 20b multiply, and add the resultant to a 40b accumulator in 80ns. Circuit permits all signal processing functions of a dual-tone multifrequency receiver or a low-speed modem to be realized on one chip.