IEEE International Workshop on Memory Technology, Design and Testing,最新文献_第2页

Design and analysis of a synchronous dram memory module 同步dram存储模块的设计与分析

IEEE International Workshop on Memory Technology, Design and Testing, Pub Date : 1996-08-13 DOI: 10.1109/MTDT.1996.782495

G. Ley, D. Phipps

引用次数: 0

Thermal monitoring of memories 记忆体热监测

IEEE International Workshop on Memory Technology, Design and Testing, Pub Date : 1996-08-13 DOI: 10.1109/MTDT.1996.782497

V. Székely, B. Courtois

引用次数: 0

Built in self testing for detection of coupling faults in semiconductor memories 内置自检测，用于检测半导体存储器中的耦合故障

IEEE International Workshop on Memory Technology, Design and Testing, Pub Date : 1996-08-13 DOI: 10.1109/MTDT.1996.782484

M. Karpovsky, D. Das, H. Vardhan

引用次数: 3

Unexpected charge losses from the floating gates of eeprom memory cells eeprom存储单元的浮动栅极的意外电荷损失

IEEE International Workshop on Memory Technology, Design and Testing, Pub Date : 1996-08-13 DOI: 10.1109/MTDT.1996.782498

R. Allinger, M. Kerber, H.J. Mattausch, H. Braun

引用次数: 2

RAM diagnostic tests RAM诊断测试

IEEE International Workshop on Memory Technology, Design and Testing, Pub Date : 1996-08-13 DOI: 10.1109/MTDT.1996.782499

V. Yarmolik, Y. Klimets, A. van de Goor, S. Demidenko

引用次数: 30

Flash memory technology - a review 闪存技术综述

IEEE International Workshop on Memory Technology, Design and Testing, Pub Date : 1996-08-13 DOI: 10.1109/MTDT.1996.782491

K. Rajkanan

{"title":"Flash memory technology - a review","authors":"K. Rajkanan","doi":"10.1109/MTDT.1996.782491","DOIUrl":"https://doi.org/10.1109/MTDT.1996.782491","url":null,"abstract":"Since the first flash memory patent issued on October 6, 1987, flash memory’s multiple useful characteristics, including nonvolatility, in-circuit reprogrammability, low power consumption, and high density, have led it to become the fastest growing memory segment in recent years. Mobile computing and communication have driven the demand for flash memories. Nascent applications, such as digital cameras, personal digital assistants (PDA), digital telephone answering devices @TAD) are expected to further add to growth in flash memory demand. Typically, flash memories are descendants of EPROM or EEPROM technologies and therefore many similarities in the architecture and operation can be noticed. As in the case of EPROMs, flash devices based on NOR architecture and the hot-electron injection mechanism for programming still dominate the marketplace. To provide erasability, the Fowler-Nordheim tunneling mechanism is typically employed. However, booming demand for flash memory has set-off a ferment of new architectures, cell structures, and manufacturing processes. For mass storage applications, NAND architecture is emerging as a contender. AND and DiNOR (Divided bit-line NOR) architectures have also emerged, each having their own advantages and disadvantages. Requirements on low power, low voltages, and higher densities have led to the development of devices which use Fowler-Nordheim tunneling for both programming and erasing. Multilevel 1087-4852/96 $5.00","PeriodicalId":228146,"journal":{"name":"IEEE International Workshop on Memory Technology, Design and Testing,","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-08-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129656462","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Flash memory quality and reliability issues 闪存质量和可靠性问题

IEEE International Workshop on Memory Technology, Design and Testing, Pub Date : 1996-08-13 DOI: 10.1109/MTDT.1996.782488

R. Verma

引用次数: 6

Proposed on-chip test structure to quantify trap densities within flash meories 提出片上测试结构以量化快闪记忆体的陷阱密度

IEEE International Workshop on Memory Technology, Design and Testing, Pub Date : 1996-08-13 DOI: 10.1109/MTDT.1996.782486

V. Verma, A. Swaneck

引用次数: 3

Giga-bit DRAM trend 千兆DRAM趋势

IEEE International Workshop on Memory Technology, Design and Testing, Pub Date : 1996-08-13 DOI: 10.1109/MTDT.1996.782490

T. Furuyama

{"title":"Giga-bit DRAM trend","authors":"T. Furuyama","doi":"10.1109/MTDT.1996.782490","DOIUrl":"https://doi.org/10.1109/MTDT.1996.782490","url":null,"abstract":"DRAM’s have been achieving higher and higher memory capacity by reducing the device sizes and complicating the memory cell structures. At present, 64M’s are available in the market and 1 GIs are under development in many semiconductor companies. Some early 1 G chips were presented at the ISSCC (International Solid State Circuits Conference) last year for the first time. DRAM’s have been also getting faster and faster as the generation has proceeded by taking an advantage of device miniaturization as well as adopting new circuit designs, such as Synchronous DRAM and Rambus technologies. Many questions have been recently raised, however, including the limit of existing memory cell technologies, how to improve speed to catch up the processor operation without blowing up the power consumption, how to realize a system that does not require as large amount of memory as the most advanced DRAM’s can provide by a single chip but requires very high data rate and performance, and so on. Test time/cost reduction is also an issue. In this presentation, I will review the state of the art DRAM technologies, functions, and circuit design topics. Trench and stacked cell technologies for 1 G DRAM’s will be compared. Different DRAM functions will be reviewed and their performances will be compared. I would also like to explore some of the issues and questions and to review some ideas recently published intending to solve these issues. The DRAM and Logic merged technology, which is presently a very hot topic in the industry and getting more and more popular, will be discussed as a candidate to provide fairly small amount of memory but high performance. Future DRAM trends from technology, function, application and other points of view, will be briefly summarized.","PeriodicalId":228146,"journal":{"name":"IEEE International Workshop on Memory Technology, Design and Testing,","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-08-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133733616","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Scanning capacitance microscopy analysis of dram trench capacitors dram沟槽电容器的扫描电容显微镜分析

IEEE International Workshop on Memory Technology, Design and Testing, Pub Date : 1996-08-13 DOI: 10.1109/MTDT.1996.782496

K. Pey, Y.E. Strausser, A. Erickson, A. Leslie, M. Beh, T. T. Sheng

引用次数: 3