{"title":"提出片上测试结构以量化快闪记忆体的陷阱密度","authors":"V. Verma, A. Swaneck","doi":"10.1109/MTDT.1996.782486","DOIUrl":null,"url":null,"abstract":"Degradation of the program/erase characteristics of Flash memory due to cycling is an industry wide reliability concern. This degradation in performance is associated with trapped charges present within the memory cells dielectric. The implementation of an on chip test structure is proposed, allowing trapping characteristics of the Flash memory cells to be monitored. This paper discusses the on-chip test structure, program/erase characteristics of Flash memories, and electron trap density measurements.","PeriodicalId":228146,"journal":{"name":"IEEE International Workshop on Memory Technology, Design and Testing,","volume":"149 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1996-08-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":"{\"title\":\"Proposed on-chip test structure to quantify trap densities within flash meories\",\"authors\":\"V. Verma, A. Swaneck\",\"doi\":\"10.1109/MTDT.1996.782486\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Degradation of the program/erase characteristics of Flash memory due to cycling is an industry wide reliability concern. This degradation in performance is associated with trapped charges present within the memory cells dielectric. The implementation of an on chip test structure is proposed, allowing trapping characteristics of the Flash memory cells to be monitored. This paper discusses the on-chip test structure, program/erase characteristics of Flash memories, and electron trap density measurements.\",\"PeriodicalId\":228146,\"journal\":{\"name\":\"IEEE International Workshop on Memory Technology, Design and Testing,\",\"volume\":\"149 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1996-08-13\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"3\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"IEEE International Workshop on Memory Technology, Design and Testing,\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/MTDT.1996.782486\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE International Workshop on Memory Technology, Design and Testing,","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/MTDT.1996.782486","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Proposed on-chip test structure to quantify trap densities within flash meories
Degradation of the program/erase characteristics of Flash memory due to cycling is an industry wide reliability concern. This degradation in performance is associated with trapped charges present within the memory cells dielectric. The implementation of an on chip test structure is proposed, allowing trapping characteristics of the Flash memory cells to be monitored. This paper discusses the on-chip test structure, program/erase characteristics of Flash memories, and electron trap density measurements.
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