IEEE International Workshop on Memory Technology, Design and Testing,最新文献

{"title":"A true testprocessor-per-pin algorithmic pattern generator","authors":"K. Hilliges, J. Sundermann","doi":"10.1109/MTDT.1996.782500","DOIUrl":"https://doi.org/10.1109/MTDT.1996.782500","url":null,"abstract":"Technical requirements and economical constraints in the semiconductor industry and particularly in the realm of memory subsystems require reevaluation of the system architecture in state of the art ATE. HP's advanced testprocessor-per-pin architecture provides a path to improved test quality by superior speed and accuracy while offering faster time to market by reducing test- engineering effort. By deploying this architecture in production test of high performance SSRAMs, the feasibility of this approach to memory test has been proven. To overcome the challenges of programming and maintaining the \"Per-Pin-APG\" patterns in production, a new high level Algorithmic Pattern Description is introduced. For uncompromised utilization of the testprocessor-per-pin architecture ALPAD pattern can be generated from the graphical user interface of the system software.","PeriodicalId":228146,"journal":{"name":"IEEE International Workshop on Memory Technology, Design and Testing,","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-08-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129560173","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A built in self test scheme for 256Meg sdram","authors":"F. Hii, T. Powell, D. Cline","doi":"10.1109/MTDT.1996.782485","DOIUrl":"https://doi.org/10.1109/MTDT.1996.782485","url":null,"abstract":"This paper presents a Built In Self Test (BIST) scheme for very high parallelism memory testing to be done on a BIST Board with DC stimuli. A BIST scheme with ten algorithms was implemented on a 256Meg, 4 banks, X32 SDRAM. Self Test operation is synchronized by an on chip oscillator which also generates internal timing signals needed for memory testing. Various ways to test the functionality of BIST circuitry as well as some engineering and debug features are also included.","PeriodicalId":228146,"journal":{"name":"IEEE International Workshop on Memory Technology, Design and Testing,","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-08-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114585496","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Future trends in flash memories","authors":"S. Grossman","doi":"10.1109/MTDT.1996.782468","DOIUrl":"https://doi.org/10.1109/MTDT.1996.782468","url":null,"abstract":"In recent years, flash memories have become the fastest growing segment of semiconductor memories. According to various analysts, the flash memory market is expected to grow at CAGR of 20%, compared to CAGR of 15% for DRAM and 10% for SRAM during 1996-1998. Some of the key applications driving this growth in flash memories are telecommunications devices, cellular telephones, modems, networking equipment, PC BIOS, disk drives, and set-top boxes. Emerging applications like digital cameras, DTAD, PDAs are also using flash memories for data storage. Further, flash is also finding its place in various new microcontrollers for leading edge embedded applications. Fueled by high volume applications such as cellular telephones, the flash market has grown to about $1.8B in 1995 from $900M in 1994 and is projected to grow to about $2.3B in 1996. Flash memory has indeed carved out a position alongside DRAM and SRAM as a key driver of memory technology. Flash memory began as a modification of the EEPROM with the realization that by erasing the entire EEPROM array at once, a lot of circuitry, including the control transistor in every cell, could be eliminated. Increased demand for flash memory has sparked the advent of numerous new cell structures, design architecture, and manufacturing processes. At present, projects using a hot electron injection based programming/Fowler-Nordheim tunnel based erase, and NOR architecture dominate the marketplace. Other architectures, such as NAND and DiNOR have also emerged. A clear trend toward single supply voltage is emerging, with some vendors offering devices which can work with both dual voltage and single voltage during write/erase operation. With the burgeoning demand for low voltage operation for applications in mobile computing and communications, low voltage and low power flash devices are inevitable. These types of devices will employ low power tunneling mechanisms for both write and erase operation. Thinner tunneling dielectrics, in conjunction with on-chip voltage pumps would be employed to lower the supply voltage requirements. For applications requiring random access, such as code/data storage for cellular phones or PC BIOS, the NOR architecture will continue to dominate. However, for mass storage application where serial access in important, the NANSD architecture will also be a contender. For low density embedded applications, where process simplification may be a higher priority over the cell size, two transistor EEPROM based flash devices will continue to be used. Memory density is primarily driven by mass storage applications. At present 16M flash devices are available, and 64M devices are around the corner. So far, flash memories have lagged one generation behind DRAM in terms of device density. However, with flash memories approaching DRAM like densities, an interesting debate has emerged-will Flash displace DRAM? In fact, ioa7-4852/96$5.00","PeriodicalId":228146,"journal":{"name":"IEEE International Workshop on Memory Technology, Design and Testing,","volume":"97 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-08-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124732648","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Design-for-test analysis of a buffered sdram dimm","authors":"S. Jandhyala, Adam W Ley","doi":"10.1109/MTDT.1996.782501","DOIUrl":"https://doi.org/10.1109/MTDT.1996.782501","url":null,"abstract":"This paper will present a design -for-test (DFT) analysis of a buffered synchronous dynamic random access memory (SDRAM) dual in-line memory module (DIMM). The analysis is restricted to board-level manufacturing faults. The test problem is described, alternate test methods are suggested, and a comparative study is presented contrasting a DFT approach including boundary-scan test - versus a non-DFT approach.","PeriodicalId":228146,"journal":{"name":"IEEE International Workshop on Memory Technology, Design and Testing,","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-08-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130717473","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Recent developments in dram testing","authors":"B. Cockburn","doi":"10.1109/MTDT.1996.782483","DOIUrl":"https://doi.org/10.1109/MTDT.1996.782483","url":null,"abstract":"The problem of designing efficient and effective tests for semiconductor memories poses a daunting challenge to the test engineer. As commodity memory capacities approach the I Gb level by the end of this decade, testing cost becomes the largest component of the total cost of production. It is therefore essential to understand the precise nature of memory defects and failure mechanisms and to therefore be in the best position to design the most economic tests. A further complication in recent years has been the proliferation of specialized memory technologies, configurations and data access modes. This presentation focusses on reviewing the important fundamental concepts and techniques that are required to design high-quality tests for testing dynamic random-access memories. Much of the memory testing literature has considered rather abstract functional fault models that appear to have little obvious justification in terms of observed faulty behaviors[1,2]. In particular much of the literature has dealt with fault models that would seem more appropriate for testing static rather than dynamic memory. The much larger production volume of DRAMs compared to that of SRAMs justifies specialized DRAM test methods. The topics covered in this presentation include the following: a brief review of DRAM architecture; DRAM-specific defects and failure mechanisms; DRAM-specific fault models; different production test types, including DC parametric, AC parametric and functional tests; tests for fault location and diagnosis; and scrambling-insensitive tests for detecting pattern-sensitivity. Recent developments in test set optimization algorithms and automatic functional test generation algorithms will also be discussed.","PeriodicalId":228146,"journal":{"name":"IEEE International Workshop on Memory Technology, Design and Testing,","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-08-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121050990","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A concurrent placement and routing strategy for improving the quality of application specific memory designs","authors":"S. Hegde","doi":"10.1109/MTDT.1996.782487","DOIUrl":"https://doi.org/10.1109/MTDT.1996.782487","url":null,"abstract":"A concurrent strategy in which placement and routing activity proceeds in parallel with circuit design and layout tasks is presented. In addition to improving the design cycle time, this strategy helps in providing an early estimate of the layout parasitics which can be used to improve the accuracy of the simulations. A 4Mb wide word DRAM has been successfully designed employing this approach.","PeriodicalId":228146,"journal":{"name":"IEEE International Workshop on Memory Technology, Design and Testing,","volume":"151 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-08-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114545846","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Methods for memory test time reduction","authors":"Wen-Jer Wu, C. Tang, M.Y. Lin","doi":"10.1109/MTDT.1996.782494","DOIUrl":"https://doi.org/10.1109/MTDT.1996.782494","url":null,"abstract":"In this paper, methods for memory test time reduction are proposed. The first part is to remove redundant test items. There are two methods proposed, one is guided by fault model and the other is by analyzing fail label (result of test). Our result shows that these two methods are just dual to each other. Their underlying problems are also proved to be polynomially equivalent to an NP- complete problem. The second part is to interconnect all test items to reuse memory states for saving initialization and verification sequences, and also settling time between two consecutive test items being applied to tester can be minimized. The interconnection problem is transformed to rural postman problem which is a famous NP- complete problem. Some heuristic algorithms are also introduced","PeriodicalId":228146,"journal":{"name":"IEEE International Workshop on Memory Technology, Design and Testing,","volume":"64 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-08-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128520070","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A low power current sensing scheme for cmos sram","authors":"H. Wang, P.C. Liu","doi":"10.1109/MTDT.1996.782489","DOIUrl":"https://doi.org/10.1109/MTDT.1996.782489","url":null,"abstract":"A low power current sensing scheme for CMOS SRAM is presented in this paper. The proposed scheme includes a modified current conveyor as the column selector, and a new designed low power current sense amplifier to sense the small differential current signals in data lines. The output of the sense amplifier is fed to a clock control RS latch both for power reduction and longer output valid time. This current sensing scheme is clocked asynchronously and the timing control circuits are also discussed. Simulation results show that a sensing speed with 3ns less is achieved by this scheme and the sensing speed is insensitive to both bit line and data line capacitances.","PeriodicalId":228146,"journal":{"name":"IEEE International Workshop on Memory Technology, Design and Testing,","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-08-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114074719","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Rambist builder: a methodology for automatic built-in self-test design of embedded rams","authors":"R. Rajsuman","doi":"10.1109/MTDT.1996.782492","DOIUrl":"https://doi.org/10.1109/MTDT.1996.782492","url":null,"abstract":"In this paper, we report a built-in self-test methodology for embedded RAMs. A CAD tool has been developed to synthesize the BIST circuitry for the compiled RAMs. The blocks such as address generator, pattern generator, multiplexers, state machine, control logic and comparator are automatically synthesized with this tool. The BIST logic is personalized to the RAM configuration and its physical bit map. This provides coverage of all stuck-at, state transition and coupling faults. In multi-port RAMs port-coupling faults are also detected. RAM addresses are generated by the address generator based upon the March algorithm. A set of multiplexers selects the path to the address, data and control lines, either from the RAM (during normal operation), or from the pattern generator (during test mode). The state machine and control logic provide signals for read, write, port selection and start/end. A comparator evaluates the data written during the write cycle against the RAM's output data to generate a pass/fail flag.","PeriodicalId":228146,"journal":{"name":"IEEE International Workshop on Memory Technology, Design and Testing,","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-08-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115566944","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A synthesizable ram bist circuit for applying an O(n log/sub 2/ n) test that detects scrambled static pattern-sensitive faults","authors":"B. Cockburn, D.P. Sarda","doi":"10.1109/MTDT.1996.782493","DOIUrl":"https://doi.org/10.1109/MTDT.1996.782493","url":null,"abstract":"In this paper we describe improvements and extensions to the BIST RAM scheme described earlier by Cockburn and Sat. The first improvement is the use of maximum transition counters, instead of binary counters or linear feedback shift registers, to generate the addresses that are used in the self-test. This change increases the ability of the tests to detect delay faults in the peripheral circuitry. The second improvement is the extension of the original scheme to use a new O(n log/sub 2/ n) test for detecting scrambled static pattern sensitive faults. The O(n log/sub 2/ n) test is similar to a test described by Franklin and Saluja; however, the new test is approximately 20% shorter. In addition, the new test is transparent; that is, the contents of a fault-free memory are restored by the time the self-test has terminated. The RAM BIST circuit for the new scheme was specified and verified using VHSIC Hardware Description Language (VHDL). Instances of the BIST circuit can be synthesized automatically for any arbitrary RAM size using commercial logic synthesis tools. As with the scheme described by Cockburn and Sat, the hardware area overhead of the new scheme is below 1% for 4 Mb RAMs and this figure drops rapidly for larger RAM sizes.","PeriodicalId":228146,"journal":{"name":"IEEE International Workshop on Memory Technology, Design and Testing,","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-08-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128171678","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}