Methods for memory test time reduction

Abstract

In this paper, methods for memory test time reduction are proposed. The first part is to remove redundant test items. There are two methods proposed, one is guided by fault model and the other is by analyzing fail label (result of test). Our result shows that these two methods are just dual to each other. Their underlying problems are also proved to be polynomially equivalent to an NP- complete problem. The second part is to interconnect all test items to reuse memory states for saving initialization and verification sequences, and also settling time between two consecutive test items being applied to tester can be minimized. The interconnection problem is transformed to rural postman problem which is a famous NP- complete problem. Some heuristic algorithms are also introduced