{"title":"用于提高特定于应用程序的内存设计质量的并发放置和路由策略","authors":"S. Hegde","doi":"10.1109/MTDT.1996.782487","DOIUrl":null,"url":null,"abstract":"A concurrent strategy in which placement and routing activity proceeds in parallel with circuit design and layout tasks is presented. In addition to improving the design cycle time, this strategy helps in providing an early estimate of the layout parasitics which can be used to improve the accuracy of the simulations. A 4Mb wide word DRAM has been successfully designed employing this approach.","PeriodicalId":228146,"journal":{"name":"IEEE International Workshop on Memory Technology, Design and Testing,","volume":"151 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1996-08-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"A concurrent placement and routing strategy for improving the quality of application specific memory designs\",\"authors\":\"S. Hegde\",\"doi\":\"10.1109/MTDT.1996.782487\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A concurrent strategy in which placement and routing activity proceeds in parallel with circuit design and layout tasks is presented. In addition to improving the design cycle time, this strategy helps in providing an early estimate of the layout parasitics which can be used to improve the accuracy of the simulations. A 4Mb wide word DRAM has been successfully designed employing this approach.\",\"PeriodicalId\":228146,\"journal\":{\"name\":\"IEEE International Workshop on Memory Technology, Design and Testing,\",\"volume\":\"151 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1996-08-13\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"IEEE International Workshop on Memory Technology, Design and Testing,\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/MTDT.1996.782487\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE International Workshop on Memory Technology, Design and Testing,","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/MTDT.1996.782487","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A concurrent placement and routing strategy for improving the quality of application specific memory designs
A concurrent strategy in which placement and routing activity proceeds in parallel with circuit design and layout tasks is presented. In addition to improving the design cycle time, this strategy helps in providing an early estimate of the layout parasitics which can be used to improve the accuracy of the simulations. A 4Mb wide word DRAM has been successfully designed employing this approach.
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