256Meg内存内置自检方案

IEEE International Workshop on Memory Technology, Design and Testing, Pub Date : 1996-08-13 DOI:10.1109/MTDT.1996.782485

F. Hii, T. Powell, D. Cline

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引用次数: 3

摘要

本文提出了一种内置自检(BIST)方案，用于在具有直流刺激的BIST板上进行非常高并行性的记忆测试。在256Meg, 4 bank, X32 SDRAM上实现了一个包含10种算法的BIST方案。自检操作由片上振荡器同步，该振荡器也产生存储器测试所需的内部定时信号。还包括测试BIST电路功能的各种方法以及一些工程和调试功能。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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A built in self test scheme for 256Meg sdram

This paper presents a Built In Self Test (BIST) scheme for very high parallelism memory testing to be done on a BIST Board with DC stimuli. A BIST scheme with ten algorithms was implemented on a 256Meg, 4 banks, X32 SDRAM. Self Test operation is synchronized by an on chip oscillator which also generates internal timing signals needed for memory testing. Various ways to test the functionality of BIST circuitry as well as some engineering and debug features are also included.

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来源期刊

IEEE International Workshop on Memory Technology, Design and Testing,

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