缓冲dram内存的设计测试分析

IEEE International Workshop on Memory Technology, Design and Testing, Pub Date : 1996-08-13 DOI:10.1109/MTDT.1996.782501

S. Jandhyala, Adam W Ley

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引用次数: 0

摘要

本文将介绍一种缓冲同步动态随机存取存储器(SDRAM)双列存储器模块(DIMM)的测试设计(DFT)分析。分析仅限于板级制造故障。对测试问题进行了描述，提出了替代测试方法，并提出了包括边界扫描测试的DFT方法与非DFT方法的比较研究。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Design-for-test analysis of a buffered sdram dimm

This paper will present a design -for-test (DFT) analysis of a buffered synchronous dynamic random access memory (SDRAM) dual in-line memory module (DIMM). The analysis is restricted to board-level manufacturing faults. The test problem is described, alternate test methods are suggested, and a comparative study is presented contrasting a DFT approach including boundary-scan test - versus a non-DFT approach.

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IEEE International Workshop on Memory Technology, Design and Testing,

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