A true testprocessor-per-pin algorithmic pattern generator

Abstract

Technical requirements and economical constraints in the semiconductor industry and particularly in the realm of memory subsystems require reevaluation of the system architecture in state of the art ATE. HP's advanced testprocessor-per-pin architecture provides a path to improved test quality by superior speed and accuracy while offering faster time to market by reducing test- engineering effort. By deploying this architecture in production test of high performance SSRAMs, the feasibility of this approach to memory test has been proven. To overcome the challenges of programming and maintaining the "Per-Pin-APG" patterns in production, a new high level Algorithmic Pattern Description is introduced. For uncompromised utilization of the testprocessor-per-pin architecture ALPAD pattern can be generated from the graphical user interface of the system software.