Design-for-test analysis of a buffered sdram dimm

Abstract

This paper will present a design -for-test (DFT) analysis of a buffered synchronous dynamic random access memory (SDRAM) dual in-line memory module (DIMM). The analysis is restricted to board-level manufacturing faults. The test problem is described, alternate test methods are suggested, and a comparative study is presented contrasting a DFT approach including boundary-scan test - versus a non-DFT approach.