{"title":"闪存质量和可靠性问题","authors":"R. Verma","doi":"10.1109/MTDT.1996.782488","DOIUrl":null,"url":null,"abstract":"The Flash memory technology uses dual layer polysilicon gate technology to store charge permanently. With the technology shrinking to smaller geometries, there comes the quality and reliability issues of the small geometry in addition to the existing memory reliability issues. The NOR flash cell architecture and its programming and erasing techniques are discussed. The paper describes some of the quality and reliability issues which exist in the flash memories today and the stresses done to evaluate those issues.","PeriodicalId":228146,"journal":{"name":"IEEE International Workshop on Memory Technology, Design and Testing,","volume":"28 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1996-08-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"6","resultStr":"{\"title\":\"Flash memory quality and reliability issues\",\"authors\":\"R. Verma\",\"doi\":\"10.1109/MTDT.1996.782488\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The Flash memory technology uses dual layer polysilicon gate technology to store charge permanently. With the technology shrinking to smaller geometries, there comes the quality and reliability issues of the small geometry in addition to the existing memory reliability issues. The NOR flash cell architecture and its programming and erasing techniques are discussed. The paper describes some of the quality and reliability issues which exist in the flash memories today and the stresses done to evaluate those issues.\",\"PeriodicalId\":228146,\"journal\":{\"name\":\"IEEE International Workshop on Memory Technology, Design and Testing,\",\"volume\":\"28 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1996-08-13\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"6\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"IEEE International Workshop on Memory Technology, Design and Testing,\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/MTDT.1996.782488\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE International Workshop on Memory Technology, Design and Testing,","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/MTDT.1996.782488","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
The Flash memory technology uses dual layer polysilicon gate technology to store charge permanently. With the technology shrinking to smaller geometries, there comes the quality and reliability issues of the small geometry in addition to the existing memory reliability issues. The NOR flash cell architecture and its programming and erasing techniques are discussed. The paper describes some of the quality and reliability issues which exist in the flash memories today and the stresses done to evaluate those issues.
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