{"title":"eeprom存储单元的浮动栅极的意外电荷损失","authors":"R. Allinger, M. Kerber, H.J. Mattausch, H. Braun","doi":"10.1109/MTDT.1996.782498","DOIUrl":null,"url":null,"abstract":"A new leakage effect, which undermines data retention on the floating gates of EEPROM memory cells, is presented. The effect was uncovered by chance, because an erase operation after high temperature bake led to the surprising result of a threshold voltage decrease, instead of the expected increase. A possible physical explanation for the responsible charge loss mechanism is given and is supported by a number of additional measurements.","PeriodicalId":228146,"journal":{"name":"IEEE International Workshop on Memory Technology, Design and Testing,","volume":"92 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1996-08-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"Unexpected charge losses from the floating gates of eeprom memory cells\",\"authors\":\"R. Allinger, M. Kerber, H.J. Mattausch, H. Braun\",\"doi\":\"10.1109/MTDT.1996.782498\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A new leakage effect, which undermines data retention on the floating gates of EEPROM memory cells, is presented. The effect was uncovered by chance, because an erase operation after high temperature bake led to the surprising result of a threshold voltage decrease, instead of the expected increase. A possible physical explanation for the responsible charge loss mechanism is given and is supported by a number of additional measurements.\",\"PeriodicalId\":228146,\"journal\":{\"name\":\"IEEE International Workshop on Memory Technology, Design and Testing,\",\"volume\":\"92 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1996-08-13\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"IEEE International Workshop on Memory Technology, Design and Testing,\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/MTDT.1996.782498\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE International Workshop on Memory Technology, Design and Testing,","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/MTDT.1996.782498","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Unexpected charge losses from the floating gates of eeprom memory cells
A new leakage effect, which undermines data retention on the floating gates of EEPROM memory cells, is presented. The effect was uncovered by chance, because an erase operation after high temperature bake led to the surprising result of a threshold voltage decrease, instead of the expected increase. A possible physical explanation for the responsible charge loss mechanism is given and is supported by a number of additional measurements.