International Conference on Simulation of Semiconductor Processes and Devices, 2003. SISPAD 2003.最新文献

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Analysis of fluctuations in ultra-small semiconductor devices 超小型半导体器件的波动分析
P. Andrei, I. Mayergoyz
{"title":"Analysis of fluctuations in ultra-small semiconductor devices","authors":"P. Andrei, I. Mayergoyz","doi":"10.1109/SISPAD.2003.1233646","DOIUrl":"https://doi.org/10.1109/SISPAD.2003.1233646","url":null,"abstract":"A technique for the analysis of fluctuations in ultra small semiconductor devices is presented. This technique is applied to the computation fluctuations of threshold voltages and terminal characteristics of MOSFET devices due to the random doping fluctuations and oxide roughness. It is based on the linearization of transport equations with respect to the fluctuating quantities. This approach completely avoids computations for many device realizations and, therefore, it is computationally much more efficient than Monte-Carlo techniques.","PeriodicalId":220325,"journal":{"name":"International Conference on Simulation of Semiconductor Processes and Devices, 2003. SISPAD 2003.","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-09-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124226447","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A novel technique for full-wave modeling of large-scale three-dimensional high-speed on/off-chip interconnect structures 一种大规模三维高速片上/片外互连结构全波建模新技术
D. Jiao, M. Mazumder, S. Chakravarty, C. Dai, M. Kobrinsky, M. Harmes, S. List
{"title":"A novel technique for full-wave modeling of large-scale three-dimensional high-speed on/off-chip interconnect structures","authors":"D. Jiao, M. Mazumder, S. Chakravarty, C. Dai, M. Kobrinsky, M. Harmes, S. List","doi":"10.1109/SISPAD.2003.1233632","DOIUrl":"https://doi.org/10.1109/SISPAD.2003.1233632","url":null,"abstract":"This paper presents a novel, rigorous, and fast method for full-wave modeling of high-speed interconnect structures. In this method, the original wave propagation problem is represented into a generalized eigenvalue problem. The resulting eigenvalue representation can comprehend conductor and dielectric losses, arbitrary dielectric and conductor configurations, and arbitrary materials such as dispersive, and anisotropic media. The edge basis function is employed to accurately represent the unknown field, and the triangular element is adopted to flexibly model arbitrary geometry. A mode-matching technique applicable to lossy system is developed to solve large-scale 3D problems by using 2D-like CPU time and memory. A circuit-based extraction technique is developed to obtain S-parameters from the unknown fields. The proposed technique can generate S-parameters, full-wave RLGC, propagation constants, characteristic impedances, voltage, current, and field distributions, and hence yield a comprehensive representation of interconnect structures. Experimental and numerical results demonstrate its accuracy and efficiency.","PeriodicalId":220325,"journal":{"name":"International Conference on Simulation of Semiconductor Processes and Devices, 2003. SISPAD 2003.","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-09-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122635538","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 38
Grain boundary effects on subthreshold behaviour in single grain boundary nano-TFTs 晶界效应对单晶界纳米tft亚阈值行为的影响
P. Walker, H. Mizuta, S. Uno, Y. Furuta
{"title":"Grain boundary effects on subthreshold behaviour in single grain boundary nano-TFTs","authors":"P. Walker, H. Mizuta, S. Uno, Y. Furuta","doi":"10.1109/SISPAD.2003.1233673","DOIUrl":"https://doi.org/10.1109/SISPAD.2003.1233673","url":null,"abstract":"A simulation model for deep trap states at grain boundaries in Poly-Si TFTs is developed. The model is used for simulation of single GB TFT devices with sub micron channel lengths. The transport physics is clarified and it is found that in short channel devices (L/sub eff/<100 nm) the single GB TFT shows improved subthreshold behaviour compared to its SOI equivalent.","PeriodicalId":220325,"journal":{"name":"International Conference on Simulation of Semiconductor Processes and Devices, 2003. SISPAD 2003.","volume":"62 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-09-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125280988","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Compact modeling of flash memory cells including substrate-bias-dependent hot-electron gate current 包括衬底偏置相关的热电子门电流的闪存单元的紧凑建模
K. Sonoda, M. Tanizawa, S. Shimizu, Y. Araki, S. Kawai, T. Ogura, S. Kobayashi, K. Ishikawa, Y. Inoui, N. Kotani
{"title":"Compact modeling of flash memory cells including substrate-bias-dependent hot-electron gate current","authors":"K. Sonoda, M. Tanizawa, S. Shimizu, Y. Araki, S. Kawai, T. Ogura, S. Kobayashi, K. Ishikawa, Y. Inoui, N. Kotani","doi":"10.1109/SISPAD.2003.1233675","DOIUrl":"https://doi.org/10.1109/SISPAD.2003.1233675","url":null,"abstract":"We propose a compact model for flash memory cells that is suitable for SPICE simulation. The model includes a hot-electron gate current model that considers not only Channel Hot Electron (CHE) injection but also CHannel Initiated Secondary ELectron (CHISEL) injection to express properly substrate bias dependence. Simulation results of both programming and erasing characteristics for 130 nm-technology flash memory cells indicate that our model is useful in designing and optimizing circuit for flash memories.","PeriodicalId":220325,"journal":{"name":"International Conference on Simulation of Semiconductor Processes and Devices, 2003. SISPAD 2003.","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-09-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125492399","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Characterization of Zener-tunneling drain leakage current in high-dose halo implants 高剂量光晕植入物中齐纳隧道漏电流的表征
Chang-hoon Choi, Shyh-Horng Yang, G. Pollack, S. Ekbote, P. Chidambaram, S. Johnson, C. Machala, R. Dutton
{"title":"Characterization of Zener-tunneling drain leakage current in high-dose halo implants","authors":"Chang-hoon Choi, Shyh-Horng Yang, G. Pollack, S. Ekbote, P. Chidambaram, S. Johnson, C. Machala, R. Dutton","doi":"10.1109/SISPAD.2003.1233655","DOIUrl":"https://doi.org/10.1109/SISPAD.2003.1233655","url":null,"abstract":"Degraded junction leakage current in scaled MOSFETs due to enhanced band-to-band tunneling (i.e. local Zener effect) is characterized based on a modified band-to-band tunneling model. To suppress the severe drain leakage current in the presence of high-dose halo implants, the impact of implant conditions on drain leakage current is estimated based on implant induced damage (point defect) profiles.","PeriodicalId":220325,"journal":{"name":"International Conference on Simulation of Semiconductor Processes and Devices, 2003. SISPAD 2003.","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-09-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125313651","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
An efficient method for frequency-domain simulation of short channel MOSFET including the non-quasistatic effect 一种有效的含非准静态效应的短沟道MOSFET频域仿真方法
Kyu-Il Lee, Chanho Lee, Hyungsoon Shin, Y. Park, H. Min
{"title":"An efficient method for frequency-domain simulation of short channel MOSFET including the non-quasistatic effect","authors":"Kyu-Il Lee, Chanho Lee, Hyungsoon Shin, Y. Park, H. Min","doi":"10.1109/SISPAD.2003.1233679","DOIUrl":"https://doi.org/10.1109/SISPAD.2003.1233679","url":null,"abstract":"In this paper, we propose an efficient method for the harmonic balance analysis of the short channel MOSFET including the non-quasistatic effect Our method is based on the charge-sheet model in the linear region and assumes that the saturation region is modulated by the external voltage instantaneously. By comparing with the current responses under large signal conditions obtained from the time-dependent two-dimensional simulator (MEDICI), it is confirmed that the proposed method is efficient and accurate for the frequency-domain analysis of the short channel MOSFET in the 0.1 /spl mu/m regime.","PeriodicalId":220325,"journal":{"name":"International Conference on Simulation of Semiconductor Processes and Devices, 2003. SISPAD 2003.","volume":"148 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-09-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115543141","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Recent advances in sparse linear solver technology for semiconductor device simulation matrices 半导体器件仿真矩阵稀疏线性求解技术的最新进展
O. Schenk, M. Hagemann, S. Rollin
{"title":"Recent advances in sparse linear solver technology for semiconductor device simulation matrices","authors":"O. Schenk, M. Hagemann, S. Rollin","doi":"10.1109/SISPAD.2003.1233648","DOIUrl":"https://doi.org/10.1109/SISPAD.2003.1233648","url":null,"abstract":"This paper discusses recent advances in the development of robust direct and iterative sparse linear solvers for general unsymmetric linear systems of equations. The primary focus is on robust methods for semiconductor device simulations matrices, but all methods presented are solely based on the structure of the matrices and can be applied to other application areas e.g. circuit simulation. Reliability, a low memory-footprint, and a short solution time are important demands for the linear solver. Currently, no black-box solver exists that can satisfy all criteria. The linear systems from semiconductor device simulations can be highly ill-conditioned and therefore quite challenging for direct and preconditioned iterative solver. In this paper, it is shown that nonsymmetric permutations and scalings aimed at placing large entries on the diagonal greatly enhance the reliability of direct and iterative methods. The numerical experiments indicate that the overall solution strategy is both reliable and very cost effective. The paper also compares the performance of some common software packages for solving general sparse systems.","PeriodicalId":220325,"journal":{"name":"International Conference on Simulation of Semiconductor Processes and Devices, 2003. SISPAD 2003.","volume":"702 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-09-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126923279","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 22
Mobility in UTB-SOI PFETS: local coordinate-based modeling with the density gradient method UTB-SOI pfet的迁移率:基于密度梯度法的局部坐标建模
D. Connelly, D. Grupp, P. Leon, D. Yergeau
{"title":"Mobility in UTB-SOI PFETS: local coordinate-based modeling with the density gradient method","authors":"D. Connelly, D. Grupp, P. Leon, D. Yergeau","doi":"10.1109/SISPAD.2003.1233635","DOIUrl":"https://doi.org/10.1109/SISPAD.2003.1233635","url":null,"abstract":"Here, for the first time, a local coordinate-based method is used to model surface acoustic phonon and thickness variation scattering in Si/SiO/sub 2/ PMOS structures using the density-gradient method. A reduction in mobility below that predicted by the electric-field based \"universal mobility\" curves for ultra-thin-body SOI devices is predicted in excellent agreement with recently published experimental data. An extension to multiple dimensions, demonstrated with some simple examples, is then applied to cylindrical devices, showing the mobility reduction of two-dimensional confinement.","PeriodicalId":220325,"journal":{"name":"International Conference on Simulation of Semiconductor Processes and Devices, 2003. SISPAD 2003.","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-09-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132550548","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
CLIMATE (chip-level intertwined metal and active temperature estimator) CLIMATE(芯片级缠绕金属和主动温度估计器)
A. Labun, T. Reeve
{"title":"CLIMATE (chip-level intertwined metal and active temperature estimator)","authors":"A. Labun, T. Reeve","doi":"10.1109/SISPAD.2003.1233628","DOIUrl":"https://doi.org/10.1109/SISPAD.2003.1233628","url":null,"abstract":"ULSI interconnect temperature is critical for electromigration risk assessment because of the exponential dependence of lifetime on temperature and for performance issues such as timing which are sensitive to temperature-dependent resistance. Steady state wire temperature is a function of Joule self-heating within the wire, heat conducted along the wire, and heat coupled from the active devices and other nearby wires through the dielectric. Chip-level estimates of wire temperatures for HP's EV79 microprocessor require rapid processing of vast circuits and thus detailed physical calculations such as those based on 3D finite element models (FEM) are inappropriate. However, temperatures on such large devices can be accurately estimated at the resolution of individual segments of wire as extracted by geometric processing of the layout given each segment's relevant geometry, connectivity to other segments, current I/sub rms/, and the thermal conductances G/sup lat/ between them.","PeriodicalId":220325,"journal":{"name":"International Conference on Simulation of Semiconductor Processes and Devices, 2003. SISPAD 2003.","volume":"110 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-09-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133300867","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Microstructure development and evolution 微观结构的发展与演变
M. Bloomfield, Y. Im, T. Cale
{"title":"Microstructure development and evolution","authors":"M. Bloomfield, Y. Im, T. Cale","doi":"10.1109/SISPAD.2003.1233627","DOIUrl":"https://doi.org/10.1109/SISPAD.2003.1233627","url":null,"abstract":"We employ a level set-based geometry tracking software using a \"grain continuum\" representation, together with models for selected IC manufacturing processes and for microstructural evolution to study the development of grain structures. We consider electroless deposition, physical vapor deposition and grain boundary migration during curvature-driven ripening. We use an \"encapsulation technique\" to convert atomistic data; e.g., from Monte Carlo simulations of nucleation, to continua for input to deposition studies.","PeriodicalId":220325,"journal":{"name":"International Conference on Simulation of Semiconductor Processes and Devices, 2003. SISPAD 2003.","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-09-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131440847","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
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