包括衬底偏置相关的热电子门电流的闪存单元的紧凑建模

International Conference on Simulation of Semiconductor Processes and Devices, 2003. SISPAD 2003. Pub Date : 2003-09-29 DOI:10.1109/SISPAD.2003.1233675

K. Sonoda, M. Tanizawa, S. Shimizu, Y. Araki, S. Kawai, T. Ogura, S. Kobayashi, K. Ishikawa, Y. Inoui, N. Kotani

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引用次数: 0

摘要

我们提出了一种适用于SPICE模拟的紧凑型闪存单元模型。该模型包括一个热电子门电流模型，该模型不仅考虑了通道热电子(CHE)注入，而且考虑了通道引发的二次电子(CHISEL)注入，以适当地表达衬底偏压依赖性。对130纳米技术闪存单元的编程和擦除特性的仿真结果表明，该模型可用于闪存电路的设计和优化。

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Compact modeling of flash memory cells including substrate-bias-dependent hot-electron gate current

We propose a compact model for flash memory cells that is suitable for SPICE simulation. The model includes a hot-electron gate current model that considers not only Channel Hot Electron (CHE) injection but also CHannel Initiated Secondary ELectron (CHISEL) injection to express properly substrate bias dependence. Simulation results of both programming and erasing characteristics for 130 nm-technology flash memory cells indicate that our model is useful in designing and optimizing circuit for flash memories.

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来源期刊

International Conference on Simulation of Semiconductor Processes and Devices, 2003. SISPAD 2003.

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