Compact modeling of flash memory cells including substrate-bias-dependent hot-electron gate current

Abstract

We propose a compact model for flash memory cells that is suitable for SPICE simulation. The model includes a hot-electron gate current model that considers not only Channel Hot Electron (CHE) injection but also CHannel Initiated Secondary ELectron (CHISEL) injection to express properly substrate bias dependence. Simulation results of both programming and erasing characteristics for 130 nm-technology flash memory cells indicate that our model is useful in designing and optimizing circuit for flash memories.