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International Conference on Simulation of Semiconductor Processes and Devices, 2003. SISPAD 2003.最新文献

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Analysis of gate currents through high-k dielectrics using a Monte Carlo device simulator [MOSFET applications] 利用蒙特卡罗器件模拟器分析高k介电介质的栅极电流[MOSFET应用]
International Conference on Simulation of Semiconductor Processes and Devices, 2003. SISPAD 2003. Pub Date : 2003-09-29 DOI: 10.1109/SISPAD.2003.1233639
Y. Ohkura, C. Suzuki, H. Amakawa, K. Nishi
{"title":"Analysis of gate currents through high-k dielectrics using a Monte Carlo device simulator [MOSFET applications]","authors":"Y. Ohkura, C. Suzuki, H. Amakawa, K. Nishi","doi":"10.1109/SISPAD.2003.1233639","DOIUrl":"https://doi.org/10.1109/SISPAD.2003.1233639","url":null,"abstract":"The gate current through high-k dielectrics has been calculated by a Monte Carlo simulator. In high-k dielectrics, the gate current from the drain edge is dominant and is quite serious due to a lowering of the barrier height with an increasing dielectric constant. The stack structure of high-k dielectric and oxide films is effective to suppress gate current densities generated from high-energy carriers generated near the drain edge.","PeriodicalId":220325,"journal":{"name":"International Conference on Simulation of Semiconductor Processes and Devices, 2003. SISPAD 2003.","volume":"1990 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-09-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130885455","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
Modeling and characterization of copper interconnects for SoC design 用于SoC设计的铜互连的建模和表征
International Conference on Simulation of Semiconductor Processes and Devices, 2003. SISPAD 2003. Pub Date : 2003-09-29 DOI: 10.1109/SISPAD.2003.1233622
N. Arora
{"title":"Modeling and characterization of copper interconnects for SoC design","authors":"N. Arora","doi":"10.1109/SISPAD.2003.1233622","DOIUrl":"https://doi.org/10.1109/SISPAD.2003.1233622","url":null,"abstract":"Interconnect (wiring) is central to nanometer system-on-a-chip (SoC) design. As such, accurate interconnect modeling and characterization are key to the design and verification of SoCs. Today copper (Cu) has become a mainstream material for on-chip interconnections. Unlike aluminum (Al) interconnects, Cu wire line width and thickness is a function of wire width and spacing, wire-pattern density, and topography. These new effects must be modeled accurately for designs to achieve first-time silicon success. In this paper, we discusses the Cu process and its impact on modeling the interconnect parasitic elements - resistance (R), capacitance (C), and inductance (L). For a given process node, the use of Cu reduces interconnect delay and power, but from a design prospective, the same effect is achieved by reducing wire length. The impact of the X-architecture, which makes pervasive use of diagonal lines and has the promise of reducing wire length by an average of 20%, is also discussed. Finally, silicon validation of the interconnect R, C, and L model, using a test-chip approach, is covered.","PeriodicalId":220325,"journal":{"name":"International Conference on Simulation of Semiconductor Processes and Devices, 2003. SISPAD 2003.","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-09-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122494606","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 16
Simulation of the circuit performance impact of lithography in nanoscale semiconductor manufacturing 纳米级半导体制造中光刻技术对电路性能影响的模拟
International Conference on Simulation of Semiconductor Processes and Devices, 2003. SISPAD 2003. Pub Date : 2003-09-29 DOI: 10.1109/SISPAD.2003.1233676
Munkang Choi, L. Milor, L. Capodieci
{"title":"Simulation of the circuit performance impact of lithography in nanoscale semiconductor manufacturing","authors":"Munkang Choi, L. Milor, L. Capodieci","doi":"10.1109/SISPAD.2003.1233676","DOIUrl":"https://doi.org/10.1109/SISPAD.2003.1233676","url":null,"abstract":"With nanoscale semiconductor technology, circuit performance is increasingly influenced by details of the manufacturing process. An increasing number of manufacturing features, which are not included in standard design tools, affect both circuit performance and yield. One source of circuit performance degradation is lithography imperfections. Therefore, we need to simulate how lithography imperfections impact circuit performance. Such imperfections include the proximity effect, lens aberrations, and flare. These imperfections in lithography impact circuit timing. This paper introduces a method to incorporate the proximity effect, lens aberrations, and flare in timing simulation. Our method involves expanding and revising the cell library by considering optical effects. ISCAS benchmark circuits are used to evaluate the circuit performance impact of each optical effect.","PeriodicalId":220325,"journal":{"name":"International Conference on Simulation of Semiconductor Processes and Devices, 2003. SISPAD 2003.","volume":"137 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-09-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123799178","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Experimental study on carrier transport mechanism in ultrathin-body SOI MOSFETs 超薄体SOI mosfet中载流子输运机制的实验研究
International Conference on Simulation of Semiconductor Processes and Devices, 2003. SISPAD 2003. Pub Date : 2003-09-29 DOI: 10.1109/SISPAD.2003.1233625
Ken Uchida, H. Watanabe, Junji Koga, Atsuhiro Kinoshita, Shinichi Takagi
{"title":"Experimental study on carrier transport mechanism in ultrathin-body SOI MOSFETs","authors":"Ken Uchida, H. Watanabe, Junji Koga, Atsuhiro Kinoshita, Shinichi Takagi","doi":"10.1109/SISPAD.2003.1233625","DOIUrl":"https://doi.org/10.1109/SISPAD.2003.1233625","url":null,"abstract":"The electrical characteristics of ultrathin-body SOI CMOSFETs are intensively investigated. It is demonstrated that electron mobility increases as SOI thickness decreases, when SOI thickness, T/sub SOI/, is in the range from 3.5 nm to 4.5 nm. On the other hand, hole mobility decreases monotonically as T/sub SOI/ decreases. In addition, it is demonstrated that, when SOI thickness is thinner than 4 nm, slight (even atomic-level) SOI thickness fluctuations have a significant impact on threshold voltage, gate-channel capacitance, and carrier mobility of ultrathin-body CMOSFETs.","PeriodicalId":220325,"journal":{"name":"International Conference on Simulation of Semiconductor Processes and Devices, 2003. SISPAD 2003.","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-09-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126801817","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 21
Zero-flux boundary condition in a two-probability-parameter random walk model 双概率参数随机游走模型的零通量边界条件
International Conference on Simulation of Semiconductor Processes and Devices, 2003. SISPAD 2003. Pub Date : 2003-09-29 DOI: 10.1109/SISPAD.2003.1233650
M. Orlowski
{"title":"Zero-flux boundary condition in a two-probability-parameter random walk model","authors":"M. Orlowski","doi":"10.1109/SISPAD.2003.1233650","DOIUrl":"https://doi.org/10.1109/SISPAD.2003.1233650","url":null,"abstract":"Zero-flux boundary condition is revisited in the context of a two-probability-para meter and a rigorous combinatorial model. The two-parameter model distinguishes partial segregation, partial absorption, and partial reflection. Both models show that vanishing flux across the barrier can be realized for non-zero gradient of the dopant distribution at the boundary.","PeriodicalId":220325,"journal":{"name":"International Conference on Simulation of Semiconductor Processes and Devices, 2003. SISPAD 2003.","volume":"75 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-09-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131343092","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Experimental studies of dopant diffusion in strained Si and SiGe 掺杂剂在应变Si和SiGe中扩散的实验研究
International Conference on Simulation of Semiconductor Processes and Devices, 2003. SISPAD 2003. Pub Date : 2003-09-29 DOI: 10.1109/SISPAD.2003.1233624
A. Larsen, N. Zangenberg
{"title":"Experimental studies of dopant diffusion in strained Si and SiGe","authors":"A. Larsen, N. Zangenberg","doi":"10.1109/SISPAD.2003.1233624","DOIUrl":"https://doi.org/10.1109/SISPAD.2003.1233624","url":null,"abstract":"Summary form only given. It is of crucial importance for modeling and simulation of physical processes, that reliable experimental information exists against which the models can be tested. Epitaxially grown semiconductor heterostructures are ideal systems for producing such information as a number of parameters can be varied such as e.g. chemical composition, and size and type of biaxial strain (tensile or compressive). The Si/SiGe epitaxial system constitutes such a system. We have over the past 10 years studied atomic diffusion in the Si/SiGe epitaxial system using molecular-beam epitaxially grown structures containing well-defined narrow distributions of the tracer impurity or isotope under investigation. The atomic profiles were measured using secondary ion mass spectrometry (SIMS), and the structural quality of the samples and their possible strain relaxation by misfit dislocations during heat treatment were examined by transmission electron microscopy (TEM).","PeriodicalId":220325,"journal":{"name":"International Conference on Simulation of Semiconductor Processes and Devices, 2003. SISPAD 2003.","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-09-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132700210","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Coupled modeling of time-dependent full-chip heating and quantum non-isothermal device operation 时变全芯片加热与量子非等温器件操作的耦合建模
International Conference on Simulation of Semiconductor Processes and Devices, 2003. SISPAD 2003. Pub Date : 2003-09-29 DOI: 10.1109/SISPAD.2003.1233699
A. Akturk, N. Goldsman, G. Metze
{"title":"Coupled modeling of time-dependent full-chip heating and quantum non-isothermal device operation","authors":"A. Akturk, N. Goldsman, G. Metze","doi":"10.1109/SISPAD.2003.1233699","DOIUrl":"https://doi.org/10.1109/SISPAD.2003.1233699","url":null,"abstract":"A method for predicting full chip temperature heating resulting from device operation is presented. The method couples distributed device simulation with lumped thermal analysis. Predictions show sixty degree Kelvin temperature increases for 0.5 cm IC's. A method for reducing chip temperature is also presented.","PeriodicalId":220325,"journal":{"name":"International Conference on Simulation of Semiconductor Processes and Devices, 2003. SISPAD 2003.","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-09-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122541298","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
A numerically efficient method for the hydrodynamic density-gradient model 水动力密度梯度模型的一种数值有效方法
International Conference on Simulation of Semiconductor Processes and Devices, 2003. SISPAD 2003. Pub Date : 2003-09-29 DOI: 10.1109/SISPAD.2003.1233687
Seonghoon Jin, Young-June Park, H. Min
{"title":"A numerically efficient method for the hydrodynamic density-gradient model","authors":"Seonghoon Jin, Young-June Park, H. Min","doi":"10.1109/SISPAD.2003.1233687","DOIUrl":"https://doi.org/10.1109/SISPAD.2003.1233687","url":null,"abstract":"We propose a quantum transport model that is a hydrodynamic extension of the density-gradient model. The governing equations are derived from the moments of the Wigner distribution function and their forms are suitable for the conventional device simulation program. The model is discretized by the control volume method with nonlinear discretizations for the electron and energy flux equations. We also developed a boundary condition for the Si/SiO/sub 2/ interface that includes the electron wavefunction penetration into the oxide to obtain more accurate C-V characteristics. As an application, we studied a 25 nm NMOSFET device. Compared with the semiclassical models, the new model predicts reduced gate capacitance about 20% and increased subthreshold slope and DIBL about 16% and 46% respectively. Compared with the density-gradient model, the on-current is increased up to 26% due to the nonlocal transport effect.","PeriodicalId":220325,"journal":{"name":"International Conference on Simulation of Semiconductor Processes and Devices, 2003. SISPAD 2003.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-09-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123910777","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
Study on cell characteristics of PRAM using the phase-change simulation 基于相变模拟的PRAM电池特性研究
International Conference on Simulation of Semiconductor Processes and Devices, 2003. SISPAD 2003. Pub Date : 2003-09-29 DOI: 10.1109/SISPAD.2003.1233674
Y. Kim, K. Lee, Won-young Chung, T. Kim, Y. Park, J. Kong
{"title":"Study on cell characteristics of PRAM using the phase-change simulation","authors":"Y. Kim, K. Lee, Won-young Chung, T. Kim, Y. Park, J. Kong","doi":"10.1109/SISPAD.2003.1233674","DOIUrl":"https://doi.org/10.1109/SISPAD.2003.1233674","url":null,"abstract":"In this paper, we present a new simulation methodology for analyzing cell characteristics of the chalcogenide based phase-change device, PRAM (Phase-change Random Access Memory), which is the future-generation non-volatile memory. Using the new simulation methodology, we analyze the effect of process variation, which is the most sensitive factor to operate the cell of PRAM.","PeriodicalId":220325,"journal":{"name":"International Conference on Simulation of Semiconductor Processes and Devices, 2003. SISPAD 2003.","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-09-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114765332","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
Simple wide-band on-chip inductor model for silicon-based RF ICs 用于硅基射频集成电路的简单宽带片上电感器模型
International Conference on Simulation of Semiconductor Processes and Devices, 2003. SISPAD 2003. Pub Date : 2003-09-29 DOI: 10.1109/SISPAD.2003.1233631
Joonho Gil, Hyungcheol Shin
{"title":"Simple wide-band on-chip inductor model for silicon-based RF ICs","authors":"Joonho Gil, Hyungcheol Shin","doi":"10.1109/SISPAD.2003.1233631","DOIUrl":"https://doi.org/10.1109/SISPAD.2003.1233631","url":null,"abstract":"In this paper, we developed a simple wide-band inductor model that contains lateral substrate resistance and capacitance to model the decrease in the series resistance at high frequencies, related to lateral coupling through the silicon substrate. The model accurately predicts the equivalent series resistance and inductance over a wide-frequency range. Since it has frequency-independent elements, the proposed model can be easily integrated in SPICE-compatible simulators. The proposed model has been verified with measured results of inductors fabricated in a 0.18 /spl mu/m 6-metal CMOS process. We also demonstrate the validity of the proposed model for shielded inductors. The proposed model shows excellent agreement with measured data over the whole frequency range.","PeriodicalId":220325,"journal":{"name":"International Conference on Simulation of Semiconductor Processes and Devices, 2003. SISPAD 2003.","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-09-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124764603","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 58
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