2013 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)最新文献_第4页

New observation on gate-induced drain leakage in Silicon nanowire transistors with Epi-Free CMOS compatible technology on SOI substrate SOI衬底上无epi - CMOS兼容技术的硅纳米线晶体管栅极诱发漏极的新观察

2013 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S) Pub Date : 2013-10-01 DOI: 10.1109/S3S.2013.6716583

Jiewen Fan, Ming Li, Xiaoyan Xu, Ru Huang

{"title":"New observation on gate-induced drain leakage in Silicon nanowire transistors with Epi-Free CMOS compatible technology on SOI substrate","authors":"Jiewen Fan, Ming Li, Xiaoyan Xu, Ru Huang","doi":"10.1109/S3S.2013.6716583","DOIUrl":"https://doi.org/10.1109/S3S.2013.6716583","url":null,"abstract":"As a promising transistors beyond 22nm technology node, Silicon nanowire (Si NW) transistor has attracted a lot of attentions recently [1]-[4]. Due to its unique gate-all-around (GAA) structure, Si NW transistor provides enhanced gate controllability and reduced sub-threshold leakage. However, gate-induced drain leakage (GIDL) as another primary leakage mechanism is still challenging [5][6]. In addition, due to the lateral parasitic bipolar junction transistor (PBJT), GIDL can be further enhanced in floating body transistors including Si NW transistor [7]. Unfortunately, few work on the origin sources and mechanism of GIDL in Si NW transistors have been reported up to now. In this paper, we have successfully fabricated Si NW transistors of high driving current with diameter down to 10nm on SOI substrate. More serious GIDL at low |Vgs| in Si NW transistor is observed compared with planar devices, which results from the strong gate-controlled longitudinal band-to-band tunneling (L-BTBT) of Si NW transistor, rather than traditional vertical BTBT in planar device. The dependence of GIDL on geometry parameters is also evaluated for further optimization.","PeriodicalId":219932,"journal":{"name":"2013 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)","volume":"128 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116863418","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 7

Three-dimensional integrated circuits with NFET and PFET on separate layers fabricated by low temperature Au/SiO2 hybrid bonding 采用Au/SiO2低温杂化键合技术制备了具有net和pet层的三维集成电路

2013 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S) Pub Date : 2013-10-01 DOI: 10.1109/S3S.2013.6716519

M. Goto, K. Hagiwara, Y. Iguchi, H. Ohtake, T. Saraya, E. Higurashi, H. Toshiyoshi, T. Hiramoto

引用次数: 6

Is high resistivity SOI wafer the substrate solution for RF System-on-Chip? 高电阻率SOI晶圆是射频片上系统的衬底解决方案吗?

2013 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S) Pub Date : 2013-10-01 DOI: 10.1109/S3S.2013.6716533

J. Raskin

{"title":"Is high resistivity SOI wafer the substrate solution for RF System-on-Chip?","authors":"J. Raskin","doi":"10.1109/S3S.2013.6716533","DOIUrl":"https://doi.org/10.1109/S3S.2013.6716533","url":null,"abstract":"Systems-on-Chip (SoC) and Systems-in-Package (SiP) are the most feasible solutions to fulfil the requirements of the new communication systems [1]. Both solutions will lead to a fundamental change in the design of analogue front-end architectures. It requires a high performance technology with devices that provide complex digital functionalities and can easily achieve operating frequencies in the GHz range. Therefore, it appears that only the best submicron CMOS technologies could provide a feasible and cost-effective integration of the communication systems. SOI MOSFET technology has demonstrated its potentialities for high frequency reaching cut-off frequencies close to 500 GHz for nMOSFETs [2] and for harsh environments (high temperature, radiations). Partially depleted (PD) SOI is now massively serving the 45-nm digital market where it is seen as a low-cost - low-power alternative to bulk Si. Fully depleted (FD) devices are also widely spread as they outperform existing semiconductor technologies for extremely low power analogue applications [3]. For RF and SoC applications, SOI also presents the major advantage of providing high resistivity (HR) substrate capabilities, leading to substantially reduced substrate losses. Substrate resistivity values higher than 1 kΩ-cm can easily be achieved and High Resistivity Silicon (HR-Si) is commonly foreseen as a promising substrate for radio frequency integrated circuits (RFIC) and mixed signal applications [4].","PeriodicalId":219932,"journal":{"name":"2013 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129303008","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Opportunities in 3D substrate bonding 3D基板粘合的机会

2013 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S) Pub Date : 2013-10-01 DOI: 10.1109/S3S.2013.6716528

T. Matthias, T. Uhrmann, V. Dragoi, P. Lindner

引用次数: 2

Parallelism and pipelining in ultra low voltage digital circuits 超低电压数字电路中的并行和流水线

2013 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S) Pub Date : 2013-10-01 DOI: 10.1109/S3S.2013.6716552

Mingoo Seok, Zhe Cao

引用次数: 0

3D hetero-integration technology with backside TSV and reliability challenges 三维异质集成技术与后TSV和可靠性的挑战

2013 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S) Pub Date : 2013-10-01 DOI: 10.1109/S3S.2013.6716516

Kang-wook Lee, M. Murugesan, T. Fukushima, T. Tanaka, M. Koyanagi

{"title":"3D hetero-integration technology with backside TSV and reliability challenges","authors":"Kang-wook Lee, M. Murugesan, T. Fukushima, T. Tanaka, M. Koyanagi","doi":"10.1109/S3S.2013.6716516","DOIUrl":"https://doi.org/10.1109/S3S.2013.6716516","url":null,"abstract":"Recently, hetero-integrated system (3-D super chip) involving memory, processor, power ICs, sensor, and photonic circuits has attracted attention owing to its high performance, highspeed communication, multi-functionality, and low power consumption . However, heterointegration of devices with different functions has many technical challenges owing to various types of size, thickness, and substrate because they were fabricated by different technologies. In addition, current 3-D integration technologies have another challenge such as high manufacturing cost and long prototyping time to achieve 3-D super chip. To realize 3-D super-chip with low-cost, high flexibility, and rapid prototyping time, we proposed die-level 3-D hetero-integration technology with fine-size backside TSV. Commercially available 2-D chips with different functions and sizes could be processed and integrated in die-level. To fabricate 3-D super chip, each functional chip should be thinned to 10-50μm thickness. However, the ultra-thin nature of Si substrate leads to several problems such as weak mechanical strength, warping, local deformation, and residual stress in the stacked die. In addition, the large CTE difference between Si substrate and Cu TSV and μ-bump is posing risks of undesired thermo-mechanical stress generation and Cu contamination. In this paper, we describe new 3-D heterointegration technology with backside TSV for realizing 3-D super chip with low-cost, high flexibility, and rapid prototyping time and address our attention on some of the most potent reliability issues such as thermo-mechanical stress, crystal defects, and Cu contamination introduced in 3-D integration processes.","PeriodicalId":219932,"journal":{"name":"2013 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)","volume":"340 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124208319","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A low power and radiation-tolerant FPGA implemented in FD SOI process 一种低功耗、耐辐射的FPGA实现FD SOI工艺

2013 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S) Pub Date : 2013-10-01 DOI: 10.1109/S3S.2013.6716566

Lihua Wu, Guoquan Zhang, Yan Zhao, Xiaowei Han, Bo Yang, Jianzhong Li, Jian Wang, Jiantou Gao, K. Zhao, Ning Li, Fang Yu, Zhong-li Liu

引用次数: 3

A 44μW/10MHz minimum power operation of 50K logic gate using 65nm SOTB devices with back gate control 采用带后门控制的65nm SOTB器件，50K逻辑门的最小功耗为44μW/10MHz

2013 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S) Pub Date : 2013-10-01 DOI: 10.1109/S3S.2013.6716586

S. Morohashi, N. Sugii, T. Iwamatsu, S. Kamohara, Y. Kato, C. Pham, K. Ishibashi

引用次数: 4

SRAM row decoder design for wide voltage range in 28nm UTBB-FDSOI 宽电压范围的28nm UTBB-FDSOI SRAM行解码器设计

2013 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S) Pub Date : 2013-10-01 DOI: 10.1109/S3S.2013.6716580

G. Suraci, B. Giraud, T. Benoist, A. Makosiej, O. Thomas

引用次数: 2

Harmonic distortion analysis of short channel junctionless nanowire transistors operating as amplifiers 用作放大器的短通道无结纳米线晶体管谐波失真分析

2013 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S) Pub Date : 2013-10-01 DOI: 10.1109/S3S.2013.6716569

R. Doria, R. Trevisoli, M. de Souza, M. Pavanello

引用次数: 3