Opportunities in 3D substrate bonding

Abstract

Vertical stacking of thin chips combined with Through-Silicon-Vias (TSVs) as interconnects is an attractive path to higher functional density of ICs. Different functional entities of a device are manufactured separately and later integrated by wafer bonding. This enables a modular device architecture and thus a modular manufacturing supply chain. Device manufacturers can focus on their core competence, e.g., designing and building the ASIC, and then add standardized modules, such as logic controllers or memory, from other manufacturers. Stacking dies enables the electrical performance of a system-on-chip, but it reduces the design time, complexity and cost significantly. Wafer bonding is a key manufacturing technology for 3D ICs. Fusion wafer bonding, which was initally developed for SOI wafer manufacturing is the most promising wafer stacking technology for 3D ICs.