采用带后门控制的65nm SOTB器件，50K逻辑门的最小功耗为44μW/10MHz

2013 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S) Pub Date : 2013-10-01 DOI:10.1109/S3S.2013.6716586

S. Morohashi, N. Sugii, T. Iwamatsu, S. Kamohara, Y. Kato, C. Pham, K. Ishibashi

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引用次数: 4

摘要

比较了65纳米SOTB和bulk的性能、泄漏和Emin。我们评估了具有相同布局模式的SOTB和bulk的环形振荡器。结果表明，工作频率可控制在6MHz ~ 40MHz范围内，睡眠模式的泄漏可降低3个数量级。通过施加可调的体偏置和电源电压，可以将50k栅极CMOS逻辑电路的能量降至4.4pJ/Hz，对应于10MHz时的44μW。在休眠模式下，逻辑门的漏电可以降低到4.2nA。

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A 44μW/10MHz minimum power operation of 50K logic gate using 65nm SOTB devices with back gate control

Performance, leakage and Emin on 65-nm SOTB and bulk were compared. We evaluated ring oscillators for SOTB and bulk with the same layout pattern. It is shown that operation frequency can be controlled from 6MHz to 40MHz, leakage of sleep mode can be decreased by 3 orders of magnitude on SOTB. By applying adjustable body bias and supply voltage depending on frequency, energy of 50k gates CMOS logic circuit can be minimized to be 4.4pJ/Hz, which corresponds to 44μW at 10MHz. Leakage of the logic gates can be reduced at 4.2nA at sleep mode.

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2013 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)

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