采用Au/SiO2低温杂化键合技术制备了具有net和pet层的三维集成电路

2013 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S) Pub Date : 2013-10-01 DOI:10.1109/S3S.2013.6716519

M. Goto, K. Hagiwara, Y. Iguchi, H. Ohtake, T. Saraya, E. Higurashi, H. Toshiyoshi, T. Hiramoto

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引用次数: 6

摘要

我们首次报道了由在不同层上制备的fet和fet直接键合形成的3D集成电路的演示。在200°C的低温下，Au/SiO2的杂化键合可以在FET工艺完成后直接连接nfet和pfet，而不会造成面积损失。通过3 μm直径的Au电极和101级的环形振荡器(RO)，我们成功地实现了3D CMOS逆变器的工作，证明了一种新的高密度集成电路3D集成的可行性。

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Three-dimensional integrated circuits with NFET and PFET on separate layers fabricated by low temperature Au/SiO2 hybrid bonding

We report the first demonstration of 3D ICs formed by the direct bonding of NFET and PFET prepared on separate layers. Hybrid bonding of Au/SiO2 at a low temperature of 200°C allows direct connection of NFETs and PFETs after completion of the FET process without area penalty. We have demonstrated successful operation of a 3D CMOS inverter bonded through 3-μm-diameter Au electrodes and a ring oscillator (RO) of 101 stages to show the feasibility of a novel 3D integration toward high-density ICs.

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2013 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)

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