2013 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)最新文献

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Delay Insensitive logic with increased fault tolerance and optimized for subthreshold operation 延迟不敏感逻辑,增加容错性,优化亚阈值操作
I. Santos, E. MacDonald
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引用次数: 0
The activation energy dependence on the electric field in UTBOX SOI FBRAM devices utboxsoi FBRAM器件中活化能对电场的依赖性
T. Nicoletti, S. Santos, K. Sasaki, J. Martino, M. Aoulaiche, E. Simoen, C. Claeys
{"title":"The activation energy dependence on the electric field in UTBOX SOI FBRAM devices","authors":"T. Nicoletti, S. Santos, K. Sasaki, J. Martino, M. Aoulaiche, E. Simoen, C. Claeys","doi":"10.1109/S3S.2013.6716570","DOIUrl":"https://doi.org/10.1109/S3S.2013.6716570","url":null,"abstract":"The dependence of the activation energy on the electric field is investigated in extensionless (underlap) UTBOX FDSOI applied as a single transistor floating body RAM. It was found that with the same gate stack it is possible to extract two different activation energies when the electric field in the hold condition is different. Higher barrier lowering induced by elevated electric field implies in higher energy trap level. The dominant mechanism behind this dependence is identified and attributed to Poole-Frenkel effect.","PeriodicalId":219932,"journal":{"name":"2013 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126761328","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
NW-TFET analog performance for different Ge source compositions 不同锗源组成下的NW-TFET模拟性能
P. Agopian, S. D. Dos Santos, F. Neves, J. Martino, A. Vandooren, R. Rooyackers, E. Simoen, C. Claeys
{"title":"NW-TFET analog performance for different Ge source compositions","authors":"P. Agopian, S. D. Dos Santos, F. Neves, J. Martino, A. Vandooren, R. Rooyackers, E. Simoen, C. Claeys","doi":"10.1109/S3S.2013.6716561","DOIUrl":"https://doi.org/10.1109/S3S.2013.6716561","url":null,"abstract":"The analog performance of hetero-junction vertical NanoWire Tunnel FETs (NW-TFETs) with different Ge source compositions (27% and 46%) is studied and compared to Si source devices. Although the NW-TFETs with the highest amount of Ge at the source present the highest transconductance (lower bandgap and higher BTBT predominance), the NW-TFETs with 27% Ge source present a better intrinsic voltage gain (AV) due to their better output conductance (less drain electric field penetration than for 46%). The Si source NW-TFET presented the worst analog behavior at lower gate bias. However, when VGS increases, smaller is its AV degradation making it equal or better than the value obtained for SiGe source devices, since in the former the Trap Assisted Tunneling (TAT) is predominant. The peculiar NW-TFET low frequency noise behavior is also presented.","PeriodicalId":219932,"journal":{"name":"2013 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128624095","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
Back bias influence on analog performance of pTFET 背偏置对晶体管模拟性能的影响
P. Agopian, F. Neves, J. Martino, A. Vandooren, R. Rooyackers, E. Simoen, C. Claeys
{"title":"Back bias influence on analog performance of pTFET","authors":"P. Agopian, F. Neves, J. Martino, A. Vandooren, R. Rooyackers, E. Simoen, C. Claeys","doi":"10.1109/S3S.2013.6716584","DOIUrl":"https://doi.org/10.1109/S3S.2013.6716584","url":null,"abstract":"In this work the back bias influence on the analog performance of tunnel-FETs is evaluated experimentally for the first time. The analysis of the transconductance, output conductance and intrinsic voltage gain (Av) was performed by comparing the pTFET behavior with a well-known pFinFET that was fabricated using the same process flow. Numerical simulations were also performed in order to explain the pTFET behavior. Although the pTFET shows to be more susceptible to the back bias condition, it also shows to present always a better Av for all bias conditions. The best result in both devices was obtained when the back bias is near 0 V and the Av difference is around 30 dB in favor of pTFET.","PeriodicalId":219932,"journal":{"name":"2013 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)","volume":"24 2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133207682","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
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