2013 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)最新文献_第3页

3D integration of high mobility InGaAs nFETs and Ge pFETs for ultra low power and high performance CMOS 用于超低功耗和高性能CMOS的高迁移率InGaAs nfet和Ge pfet的3D集成

2013 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S) Pub Date : 2013-10-01 DOI: 10.1109/S3S.2013.6716513

T. Irisawa, M. Oda, Y. Kamimuta, Y. Moriyama, K. Ikeda, E. Mieda, W. Jevasuwan, T. Maeda, O. Ichikawa, T. Osada, M. Hata, T. Tezuka

引用次数: 3

A sub-threshold halo implanted MOS implementation of Izhikevich neuron model 亚阈值晕植入MOS实现Izhikevich神经元模型

2013 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S) Pub Date : 2013-10-01 DOI: 10.1109/S3S.2013.6716556

Odilon O. Dutra, Gustavo D. Colleta, L. H. C. Ferreira, T. Pimenta

引用次数: 2

The first SOTB implementation of Flex Power FPGA Flex Power FPGA的第一个SOTB实现

2013 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S) Pub Date : 2013-10-01 DOI: 10.1109/S3S.2013.6716541

H. Koike, Chao Ma, M. Hioki, Y. Ogasahara, Takashi Kawanami, T. Tsutsumi, T. Nakagawa, T. Sekigawa

引用次数: 6

Three-dimensional wafer stacking using Cu TSV integrated with 45nm high performance SOI-CMOS embedded DRAM technology 三维晶圆堆叠采用Cu TSV集成45纳米高性能SOI-CMOS嵌入式DRAM技术

2013 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S) Pub Date : 2013-10-01 DOI: 10.1109/S3S.2013.6716515

P. Batra, D. LaTulipe, S. Skordas, K. Winstel, C. Kothandaraman, B. Himmel, G. Maier, B. He, Deepal Wehella Gamage, J. Golz, Wei Lin, T. Vo, D. Priyadarshini, A. Hubbard, Kristian Cauffman, B. Peethala, J. Barth, T. Kirihata, T. Graves-abe, N. Robson, S. Iyer

{"title":"Three-dimensional wafer stacking using Cu TSV integrated with 45nm high performance SOI-CMOS embedded DRAM technology","authors":"P. Batra, D. LaTulipe, S. Skordas, K. Winstel, C. Kothandaraman, B. Himmel, G. Maier, B. He, Deepal Wehella Gamage, J. Golz, Wei Lin, T. Vo, D. Priyadarshini, A. Hubbard, Kristian Cauffman, B. Peethala, J. Barth, T. Kirihata, T. Graves-abe, N. Robson, S. Iyer","doi":"10.1109/S3S.2013.6716515","DOIUrl":"https://doi.org/10.1109/S3S.2013.6716515","url":null,"abstract":"For high-volume production of 3D-stacked chips with through-silicon-via (TSVs), wafer-scale bonding offers lower production cost compared with bump bond technology [1][2][3] and is promising for interconnect pitch <;= 5μ range using available tooling. Prior work [3] has presented wafer-scale integration with tungsten TSV for low-power applications. This paper reports the first use of low-temperature oxide bonding and copper TSV to stack high performance cache cores manufactured in 45nm SOI-CMOS embedded DRAM (EDRAM) having 12 to 13 copper wiring levels per strata. A key feature of this process is its compatibility with the existing high performance POWER7™ EDRAM core [4] requiring neither re-design nor modification of the existing CMOS fabrication process. Hardware measurements show no significant impact on device drive and off-current. Functional test at wafer level confirms 1.48GHz 3D stacked EDRAM operation.","PeriodicalId":219932,"journal":{"name":"2013 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124012036","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 30

Scaling perspectives of ULV microcontroller cores to 28nm UTBB FDSOI CMOS uv微控制器核心到28nm UTBB FDSOI CMOS的缩放前景

2013 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S) Pub Date : 2013-10-01 DOI: 10.1109/S3S.2013.6716553

G. de Streel, D. Bol

引用次数: 5

A Double-Feedback 8T SRAM bitcell for low-voltage low-leakage operation 双反馈8T SRAM位单元，用于低压低漏操作

2013 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S) Pub Date : 2013-10-01 DOI: 10.1109/S3S.2013.6716565

Afik Vaknin, O. Yona, A. Teman

{"title":"A Double-Feedback 8T SRAM bitcell for low-voltage low-leakage operation","authors":"Afik Vaknin, O. Yona, A. Teman","doi":"10.1109/S3S.2013.6716565","DOIUrl":"https://doi.org/10.1109/S3S.2013.6716565","url":null,"abstract":"Power supply scaling is one the most common and efficient approaches for achieving low-power operation, as both static and dynamic power consumption are aggressively reduced. Ultra-low power systems are often targeted at low-voltage operation, near or below the device threshold voltage (VT). However, the design of such systems must overcome the inherent reduction of noise margins associated with lowering the supply, and in particular, the depleted noise margins of standard SRAM circuits. The two-port 8T SRAM bitcell has been a popular choice for the implementation of low-voltage embedded memories, due to its decoupled read buffer that solves much of the read margin limitation of the standard 6T SRAM cell [1]. However, the 8T circuit is still limited by write margin, and in addition, does not support half-select operations, which are a requirement of many systems. Another disadvantage of the 6T and 8T circuits is that in standby, they present several transistors with relatively high leakage paths through them, leading to significant static power dissipation. In this paper, we propose a novel Double-Feedback SRAM (DF-SRAM) bitcell with improved write margins for low-voltage operation, reduced leakage for ultra-low power consumption, and improved half-select support.","PeriodicalId":219932,"journal":{"name":"2013 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128429264","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 6

DTMOS power switch in 28 nm UTBB FD-SOI technology 采用28nm UTBB FD-SOI技术的DTMOS电源开关

2013 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S) Pub Date : 2013-10-01 DOI: 10.1109/S3S.2013.6716542

J. Le Coz, B. Pelloux-Prayer, B. Giraud, F. Giner, P. Flatresse

引用次数: 9

High temperature and radiation hard CMOS SOI sub-threshold voltage reference 高温和辐射硬CMOS SOI亚阈值电压基准

2013 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S) Pub Date : 2013-10-01 DOI: 10.1109/S3S.2013.6716543

E. Boufouss, P. Gérard, P. Simon, L. Francis, D. Flandre

引用次数: 8

Suppression of self-heating effect employing bulk vertical-channel bipolar junction transistor (BJT) type capacitorless 1T-DRAM cell 采用体垂直通道双极结晶体管(BJT)型无电容1T-DRAM电池抑制自热效应

2013 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S) Pub Date : 2013-10-01 DOI: 10.1109/S3S.2013.6716574

T. Imamoto, T. Endoh

引用次数: 1

Practical process flows for monolithic 3D 实际工艺流程的整体3D

2013 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S) Pub Date : 2013-10-01 DOI: 10.1109/S3S.2013.6716512

Z. Or-Bach

引用次数: 3