用于超低功耗和高性能CMOS的高迁移率InGaAs nfet和Ge pfet的3D集成

2013 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S) Pub Date : 2013-10-01 DOI:10.1109/S3S.2013.6716513

T. Irisawa, M. Oda, Y. Kamimuta, Y. Moriyama, K. Ikeda, E. Mieda, W. Jevasuwan, T. Maeda, O. Ichikawa, T. Osada, M. Hata, T. Tezuka

{"title":"用于超低功耗和高性能CMOS的高迁移率InGaAs nfet和Ge pfet的3D集成","authors":"T. Irisawa, M. Oda, Y. Kamimuta, Y. Moriyama, K. Ikeda, E. Mieda, W. Jevasuwan, T. Maeda, O. Ichikawa, T. Osada, M. Hata, T. Tezuka","doi":"10.1109/S3S.2013.6716513","DOIUrl":null,"url":null,"abstract":"InGaAs/Ge stacked 3D CMOS inverters have been successfully demonstrated down to Vdd = 0.2 V. The negligible degradation of the top and the bottom device characteristics indicates high technical feasibility of the InGaAs/Ge stacked 3D integration for ultra low-power and high performance CMOS.","PeriodicalId":219932,"journal":{"name":"2013 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2013-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":"{\"title\":\"3D integration of high mobility InGaAs nFETs and Ge pFETs for ultra low power and high performance CMOS\",\"authors\":\"T. Irisawa, M. Oda, Y. Kamimuta, Y. Moriyama, K. Ikeda, E. Mieda, W. Jevasuwan, T. Maeda, O. Ichikawa, T. Osada, M. Hata, T. Tezuka\",\"doi\":\"10.1109/S3S.2013.6716513\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"InGaAs/Ge stacked 3D CMOS inverters have been successfully demonstrated down to Vdd = 0.2 V. The negligible degradation of the top and the bottom device characteristics indicates high technical feasibility of the InGaAs/Ge stacked 3D integration for ultra low-power and high performance CMOS.\",\"PeriodicalId\":219932,\"journal\":{\"name\":\"2013 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)\",\"volume\":\"31 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2013-10-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"3\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2013 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/S3S.2013.6716513\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2013 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/S3S.2013.6716513","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 3

摘要

InGaAs/Ge堆叠3D CMOS逆变器已经成功地演示了Vdd = 0.2 V。顶部和底部器件特性的退化可以忽略不计，这表明超低功耗高性能CMOS InGaAs/Ge堆叠3D集成技术具有很高的技术可行性。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

查看原文本刊更多论文

3D integration of high mobility InGaAs nFETs and Ge pFETs for ultra low power and high performance CMOS

InGaAs/Ge stacked 3D CMOS inverters have been successfully demonstrated down to Vdd = 0.2 V. The negligible degradation of the top and the bottom device characteristics indicates high technical feasibility of the InGaAs/Ge stacked 3D integration for ultra low-power and high performance CMOS.

求助全文

通过发布文献求助，成功后即可免费获取论文全文。去求助

来源期刊

2013 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)

自引率

0.00%

发文量