一种低功耗、耐辐射的FPGA实现FD SOI工艺

2013 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S) Pub Date : 2013-10-01 DOI:10.1109/S3S.2013.6716566

Lihua Wu, Guoquan Zhang, Yan Zhao, Xiaowei Han, Bo Yang, Jianzhong Li, Jian Wang, Jiantou Gao, K. Zhao, Ning Li, Fang Yu, Zhong-li Liu

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引用次数: 3

摘要

提出了一种采用0.2μm全损耗绝缘体上硅(FD SOI)工艺制作的33万栅极现场可编程门阵列(FPGA) VS12C芯片，测试结果表明，与采用0.22μm外延硅制作的赛灵思抗辐射XQVR300芯片相比，该芯片具有更低的功耗和更高的抗辐射能力。本文论证了FD SOI技术在低功耗、耐辐射FPGA电路设计中的优势。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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A low power and radiation-tolerant FPGA implemented in FD SOI process

A 330,000 gate field programmable gate array (FPGA) VS12C fabricated on 0.2μm full-depletion silicon-on-insulator (FD SOI) process is presented and the test results indicate this chip has the lower power and higher tolerance to radiation compared with Xilinx radiation-hardened XQVR300 chip implemented on 0.22μm epitaxial silicon. This paper demonstrates the benefit of the FD SOI technology on low power and radiation-tolerant FPGA circuit design.

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来源期刊

2013 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)

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