宽电压范围的28nm UTBB-FDSOI SRAM行解码器设计

2013 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S) Pub Date : 2013-10-01 DOI:10.1109/S3S.2013.6716580

G. Suraci, B. Giraud, T. Benoist, A. Makosiej, O. Thomas

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引用次数: 2

摘要

本文重点研究了基于28纳米超薄体和埋藏氧化物(UTBB)全耗尽SOI (FDSOI)技术的现代便携式SRAM行解码器的设计。与常规Vt (RVT)设计相比，所提出的混合单井(Mixed- sw)设计理念能够在宽电压范围内大幅提高速度，且没有待机功率损失。仿真结果表明，混合sw双端口SRAM行解码器在1V和0.5V下的传输延迟分别降低了16%和57%。在RVT设计备用功率下获得的增益是通过宽范围n -井反向偏置实现的。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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SRAM row decoder design for wide voltage range in 28nm UTBB-FDSOI

This paper focuses on the design of SRAM row decoder for modern portable devices, in 28nm Ultra-Thin Body and Buried oxide (UTBB) Fully-Depleted SOI (FDSOI) technology. The proposed Mixed Single Well (Mixed-SW) design concept enables a major speed improvement over a wide voltage range with no standby power penalty, as compared to a regular Vt (RVT) design. The simulation results of a Mixed-SW dual-port SRAM row decoder show 16% and 57% propagation delay reduction at 1V and 0.5V, respectively. The gain obtained at RVT design standby power is enabled by the wide range N-Well back biasing.

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2013 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)

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