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The Third Annual Atlantic Test Workshop最新文献

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Integration Of Comprehensive Testing In Microelectronics Curriculum 微电子学课程综合测试的整合
The Third Annual Atlantic Test Workshop Pub Date : 2002-08-06 DOI: 10.1109/ATW.1994.747839
K. Prasad, A. Goel
{"title":"Integration Of Comprehensive Testing In Microelectronics Curriculum","authors":"K. Prasad, A. Goel","doi":"10.1109/ATW.1994.747839","DOIUrl":"https://doi.org/10.1109/ATW.1994.747839","url":null,"abstract":"This paper presents the issues pertinent to Microelectronics/VLSI Education in general, and comprehensive Testing, in particular. Integrated Circuit design employing modem testing methodologies plays a central role in microelectronics and encompasses multiple levels of abstraction: physics, chemistry, logic design, computer architecture and so forth. The Microelectronics/VLSI Educator is challenged to transcend these disparate disciplines and transform an idea into the detailed specifications for a manufactured chip(system). The system must be decomposed into subsystem, subsystem into modules, modules into components, along with exhaustive testing at each stage.","PeriodicalId":217615,"journal":{"name":"The Third Annual Atlantic Test Workshop","volume":"127 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127083144","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
The Register Optimization Step In A Self-testing High-level Synthesis Tool. 自测试高级合成工具中的寄存器优化步骤。
The Third Annual Atlantic Test Workshop Pub Date : 2002-08-06 DOI: 10.1109/ATW.1994.747845
B. Grimal, E. Martin
{"title":"The Register Optimization Step In A Self-testing High-level Synthesis Tool.","authors":"B. Grimal, E. Martin","doi":"10.1109/ATW.1994.747845","DOIUrl":"https://doi.org/10.1109/ATW.1994.747845","url":null,"abstract":"T h e au to im at i c se 1 f te s t a b 1 e architecture synthesis consists of generating a cost optimized archilecture responding to the user's constriflnts (real time and dependability constraints). The implementation of selftesting into an arclhitecture introduces an increase of its cost. \"[his increase depends on the dependability constrant specified by the conceptor. The self-testable architectures, synthesized by these tools, are cost optimized. The synthesis must include some optimization techniques of the self-testing in order to reach the dependability constraint with a minimum overhead. An automatic self-testable architectural synthesis tool niust satisfy two opposite notions : to synthesize a cost optimized architecture and to reach the dependability constraint. In this article, we will present a register optimization method whichi is adapted to self-testable architectural synthesis tools. This method allows a determination of the self-testing before the register optimization step.","PeriodicalId":217615,"journal":{"name":"The Third Annual Atlantic Test Workshop","volume":"125 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133009540","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Designing For Space Applications Usinlg The SET Concept 运用SET概念进行空间应用设计
The Third Annual Atlantic Test Workshop Pub Date : 2002-08-06 DOI: 10.1109/ATW.1994.747836
K. J. Hein, A. Rucinski
{"title":"Designing For Space Applications Usinlg The SET Concept","authors":"K. J. Hein, A. Rucinski","doi":"10.1109/ATW.1994.747836","DOIUrl":"https://doi.org/10.1109/ATW.1994.747836","url":null,"abstract":"To keep pace with technological changes prevalent in engineering today, the academic community must devise novel approaches to bridge the gap between academia and industry. The student Engineering leam (SET) concept presented in this paper addresses this issue without major restructuring of current curricula, It is illustrated by describing a student project which involves the development of a VLSI chip for the NASA/ESA Equator-S program.","PeriodicalId":217615,"journal":{"name":"The Third Annual Atlantic Test Workshop","volume":"53 3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114524864","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Introduction Of Identification In Protocol Certification 协议认证中的身份识别介绍
The Third Annual Atlantic Test Workshop Pub Date : 2002-08-06 DOI: 10.1109/ATW.1994.747848
C. Baron, J. Geffroy
{"title":"Introduction Of Identification In Protocol Certification","authors":"C. Baron, J. Geffroy","doi":"10.1109/ATW.1994.747848","DOIUrl":"https://doi.org/10.1109/ATW.1994.747848","url":null,"abstract":"This paper shows how formal identification methods can be applied to communication protocol validation. First the general context of protocol certification is presented according to two points of view: design verification and implementation testing. Then we introduce identification principles and their applications. Last we show the applicability of identification at different levels of conformance testing.","PeriodicalId":217615,"journal":{"name":"The Third Annual Atlantic Test Workshop","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124108295","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Application Of Software Test Methods For Hardware Testing 软件测试方法在硬件测试中的应用
The Third Annual Atlantic Test Workshop Pub Date : 2002-08-06 DOI: 10.1109/ATW.1994.747833
R. Liyanage, E. W. Czeck
{"title":"Application Of Software Test Methods For Hardware Testing","authors":"R. Liyanage, E. W. Czeck","doi":"10.1109/ATW.1994.747833","DOIUrl":"https://doi.org/10.1109/ATW.1994.747833","url":null,"abstract":"This paper presents a behavioral-level test generation technique for VHDL models using data-domain and path extraction. To automate the data-domain method, algorithms for VHDL basic operations are developed. These algorithms are applied to several behavioral-VHDL specifications and an evaluation comparing test length and gate-level fault coverage is performed.","PeriodicalId":217615,"journal":{"name":"The Third Annual Atlantic Test Workshop","volume":"59 3","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134127350","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
SPECIAL : a Specification Language for Generation of VHDL Behavioral Descriptions SPECIAL:用于生成VHDL行为描述的规范语言
The Third Annual Atlantic Test Workshop Pub Date : 2002-08-06 DOI: 10.1109/ATW.1994.747826
N. Valverde, A. Courbis, J. Santucci, A. Rucinski
{"title":"SPECIAL : a Specification Language for Generation of VHDL Behavioral Descriptions","authors":"N. Valverde, A. Courbis, J. Santucci, A. Rucinski","doi":"10.1109/ATW.1994.747826","DOIUrl":"https://doi.org/10.1109/ATW.1994.747826","url":null,"abstract":"In Existing Cad Methodologies The Linkage Between The Microelectronic System Specification Arsd Vhdl Design Tools Is Not Yet Clearly Defined. The Presence Of A Design Environment Which Would Estiminate This Deficiency Will Substantially Shorten The Design Development Cycle As Well As Enhance Its Reusability Aspect. The Described Design Specification Language, Special, Allows A Designer To Represent The Initial Stage Of A Microelectronic System In A Graphical Form. The Corresponding Vhdl Behavioral Description Is Then Automatically Generated. The Concept Of This Design Methodology Is Unique In Two Aspects: (i) The Timing Considerations Are Fully Integrated, And (ii) The Custom-specific Design Habits Are Easy To Incorporate And Modify.","PeriodicalId":217615,"journal":{"name":"The Third Annual Atlantic Test Workshop","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115768235","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
VOICE: Virtual Organizations Through Inter-networked Collaborative Environments 网络协作环境下的虚拟组织
The Third Annual Atlantic Test Workshop Pub Date : 2002-08-06 DOI: 10.1109/ATW.1994.747837
B. Dziurla-Rucinska, W. Niebel, D. Brousseau
{"title":"VOICE: Virtual Organizations Through Inter-networked Collaborative Environments","authors":"B. Dziurla-Rucinska, W. Niebel, D. Brousseau","doi":"10.1109/ATW.1994.747837","DOIUrl":"https://doi.org/10.1109/ATW.1994.747837","url":null,"abstract":"A traditional academic scenario in which interactions among players are couducted at a designated location is studied. This teaching approach is replaced by a setting in which the requirement of continuous presence at the same place is no longer valid. Wide area computer networks not only provide a global communication medium, but also the least expeosive one. The VOICE (Virtual Organizations through Internetworked Collaborative Environments) software, developed at the University of New Hampshire, represents a robust and a low-cost environment which facilitates activities among participants dispersed around the globe. To validate the VOICE concept, a prototyping educational experiment is described between the University of New Hampshire, U.S.A. and the Technical University of Budapest, Hungary.","PeriodicalId":217615,"journal":{"name":"The Third Annual Atlantic Test Workshop","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125734572","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
New Testability Measures For High Level Description Of Circuits 电路高级描述的新可测试性措施
The Third Annual Atlantic Test Workshop Pub Date : 2002-08-06 DOI: 10.1109/ATW.1994.747842
M. Gentil, D. Crestani, A. Rhalibi, C. Durante
{"title":"New Testability Measures For High Level Description Of Circuits","authors":"M. Gentil, D. Crestani, A. Rhalibi, C. Durante","doi":"10.1109/ATW.1994.747842","DOIUrl":"https://doi.org/10.1109/ATW.1994.747842","url":null,"abstract":"This paper proposes high level testabillty measures based on constraints propagation approach and symbolic fault modelling. These measures are compared with some others on a circuit example poinung out their accunacy to show the circuit areas which are difficult to test.","PeriodicalId":217615,"journal":{"name":"The Third Annual Atlantic Test Workshop","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125114995","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
V.L.S.I. diagnosis using high level knowledge V.L.S.I.诊断使用高水平的知识
The Third Annual Atlantic Test Workshop Pub Date : 2002-08-06 DOI: 10.1109/ATW.1994.747843
P. Chardon, C. Durante
{"title":"V.L.S.I. diagnosis using high level knowledge","authors":"P. Chardon, C. Durante","doi":"10.1109/ATW.1994.747843","DOIUrl":"https://doi.org/10.1109/ATW.1994.747843","url":null,"abstract":"7 1 s aper introduces, a useful and effective method for VLSI dagnosis based on a theorem concerning the Boolean Difference part 2). I t , & a high level diagnosis method for high f eve1 circuits. First, modules are considered (part 3). hks between miodules are d e f i e d art 4 5)\"and. tLe more general w e is described (part 6 Y before condusion (part 7)1.","PeriodicalId":217615,"journal":{"name":"The Third Annual Atlantic Test Workshop","volume":"125 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116846410","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Fault modeling and injection in vital descriptions 关键描述中的故障建模和注入
The Third Annual Atlantic Test Workshop Pub Date : 2002-08-06 DOI: 10.1109/ATW.1994.747841
V. Fernández, P. Sánchez, M. García, E. Villar
{"title":"Fault modeling and injection in vital descriptions","authors":"V. Fernández, P. Sánchez, M. García, E. Villar","doi":"10.1109/ATW.1994.747841","DOIUrl":"https://doi.org/10.1109/ATW.1994.747841","url":null,"abstract":"In this paper a fault model for VHDL descriptions following the VITAL guidelines is permitted. Fault injection in the elaborated model of the VHDL descriptions are also going to be presented in tis paper.","PeriodicalId":217615,"journal":{"name":"The Third Annual Atlantic Test Workshop","volume":"141 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122916640","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
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