SPECIAL:用于生成VHDL行为描述的规范语言

N. Valverde, A. Courbis, J. Santucci, A. Rucinski
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引用次数: 0

摘要

在现有的Cad方法中,微电子系统规范与Vhdl设计工具之间的联系尚未明确定义。设计环境的存在可以估计这种缺陷,这将大大缩短设计开发周期,并提高其可重用性。所描述的设计规范语言,特殊,允许设计者以图形形式表示微电子系统的初始阶段。然后自动生成相应的Vhdl行为描述。这种设计方法的概念在两个方面是独特的:(i)时间考虑是完全集成的;(ii)定制的特定设计习惯是容易合并和修改的。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
SPECIAL : a Specification Language for Generation of VHDL Behavioral Descriptions
In Existing Cad Methodologies The Linkage Between The Microelectronic System Specification Arsd Vhdl Design Tools Is Not Yet Clearly Defined. The Presence Of A Design Environment Which Would Estiminate This Deficiency Will Substantially Shorten The Design Development Cycle As Well As Enhance Its Reusability Aspect. The Described Design Specification Language, Special, Allows A Designer To Represent The Initial Stage Of A Microelectronic System In A Graphical Form. The Corresponding Vhdl Behavioral Description Is Then Automatically Generated. The Concept Of This Design Methodology Is Unique In Two Aspects: (i) The Timing Considerations Are Fully Integrated, And (ii) The Custom-specific Design Habits Are Easy To Incorporate And Modify.
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