The Register Optimization Step In A Self-testing High-level Synthesis Tool.

T h e au to im at i c se 1 f te s t a b 1 e architecture synthesis consists of generating a cost optimized archilecture responding to the user's constriflnts (real time and dependability constraints). The implementation of selftesting into an arclhitecture introduces an increase of its cost. "[his increase depends on the dependability constrant specified by the conceptor. The self-testable architectures, synthesized by these tools, are cost optimized. The synthesis must include some optimization techniques of the self-testing in order to reach the dependability constraint with a minimum overhead. An automatic self-testable architectural synthesis tool niust satisfy two opposite notions : to synthesize a cost optimized architecture and to reach the dependability constraint. In this article, we will present a register optimization method whichi is adapted to self-testable architectural synthesis tools. This method allows a determination of the self-testing before the register optimization step.