The Third Annual Atlantic Test Workshop最新文献

{"title":"Recovery And Enhancement Of System Patterns Infoschemata And Infomaps","authors":"W. M. Jaworski, A. Michailidis","doi":"10.1109/ATW.1994.747828","DOIUrl":"https://doi.org/10.1109/ATW.1994.747828","url":null,"abstract":"Evolving systems demand technology transfer. Knowledge is the most important ingredient in technology transfer. However, the creation of knowledge is a complex, slow and expensive process. Recovery and enhancement of knowledge from existing systems for integration into evolving systems is the logical and more attractive approach. Most of system research and development generates complex concepts. A need for the development of schemata in a multidimensional environment is more evident now than ever before. Team work could be converted from a single to a multi-tasking environment and enable developers to perform tasks concurrently. This paper presents the underlying principles for the recovery and development of reusable system patterns. The proposed approach supports crossfunctional development teams, multidimensional modeling and concurrent engineering paradigms. The evolving model of recovering and analyzing existing patterns is described. This model attempts to minimize the conceptual complexity of systems by identifying and abstracting schemata. The analysis performed on the original concepts and methodologies enables the discovery and integration of simple schemata into a library of reusable patterns. The application of a knowledge recovery process to object-oriented methodologies, CASE tools and development of a patterns library is also presented.","PeriodicalId":217615,"journal":{"name":"The Third Annual Atlantic Test Workshop","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126322811","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Fault modeling andsimulation based on VHDL","authors":"L. Entrena, J. Lopez, S. Olenz","doi":"10.1109/ATW.1994.747831","DOIUrl":"https://doi.org/10.1109/ATW.1994.747831","url":null,"abstract":"This paper presents the work related with fault modeling and simulation of VHDL descriptions under development in the ESIP project. The probletms of fault modeling and simulation are addressed from the perspective of using VHDL. Thisf approach takes advantage of the VHDL features that make possible the use of hierarchy and occurrence in fault simuiation and considers the VHDL interactive-processes simulatio straegy.","PeriodicalId":217615,"journal":{"name":"The Third Annual Atlantic Test Workshop","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127066100","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Identification Methods And Conformance Testing","authors":"C. Baron, J. Geffroy","doi":"10.1109/ATW.1994.747827","DOIUrl":"https://doi.org/10.1109/ATW.1994.747827","url":null,"abstract":"This paper places protocol test generation methods in the general context of identification approach. After a classification of identification based test generation methods, we show up how identification is used for protocol test generation and where existing methods already used for communication protocols can be linked to this classification. Identification methods being of high complexity, we suggest to take advantage of the system structure to improve the test generation and validation process. KEWORDS. Identification, Finite-State Machine, Test Generation, Test Validation, Distinguishing Sequence, W-method, UJOS.","PeriodicalId":217615,"journal":{"name":"The Third Annual Atlantic Test Workshop","volume":"52 3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134537104","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Industry/unilversity Collaboration To Design Portable Layout Generators","authors":"A. Greiner, L. Lucas, F. Pétrot, F. Wajsburt","doi":"10.1109/ATW.1994.747840","DOIUrl":"https://doi.org/10.1109/ATW.1994.747840","url":null,"abstract":"This article presents a case study of a cooperation between a company and university in the framework of the EEC IDPS project, from the point of view of the university. This project aims at providutg a `Common Library' of cells and macro-blocks for VLSI design available from all partners. An agreed level of portability rrum be defined to ensure sharing of the library by all the partners. A methodology oriented toward generator portability at the layout level has been defined, The layout p[acement uses a tiler and leaf cell approach to achieve high densities and performances. Software portability Measured by the use of the general purpose C language as tiling language. Process independence is warranted by the use of a fixed grid symbolic layout methodology, for leaf cell design. Six CMOS generators have been successfully designed following this methodology.","PeriodicalId":217615,"journal":{"name":"The Third Annual Atlantic Test Workshop","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116926866","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Functional Test Generation For finite State Machines With Concurrent Fault Simulation","authors":"N. Cooray, E. W. Czeck","doi":"10.1109/ATW.1994.747832","DOIUrl":"https://doi.org/10.1109/ATW.1994.747832","url":null,"abstract":"This paper presents a new test-sequence generation method for finite state machines at the functional specification level. The test generation algorithm incorporates concurrent functional fault simulation to reduce the length of the generated test sequence and the test generation time. The test sequence generator guarantees 100 % transition fault coverage. We also identified some weaknesses in the transil.ion fault model for finite state machines which results in less than perfect structural fault coverage.","PeriodicalId":217615,"journal":{"name":"The Third Annual Atlantic Test Workshop","volume":"423 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121823426","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Tme scaled high-level synthesis for pipelined data-flow structures","authors":"P. Arató, A. Rucinski, I. Jankovitz","doi":"10.1109/ATW.1994.747846","DOIUrl":"https://doi.org/10.1109/ATW.1994.747846","url":null,"abstract":"Since integrated circle fabrication technology has reached the level of the million transistors. it has became more urgent to introduce new approaches of system level synthesis. In parallei that the set of the available basic elements are becoming more complex. as the processors have been widely applied. The High-Level Synthesis ( FILS ) provides a direction these problems can be handled with. A desirable feature of a design process using HLS is to minirnize its dependence on technology. The nature of the design tools has changed from simple assistance during the design flow, to sophisticated knowledge source, such as providing the designer with information about important tradeoffs determined by the application. .An intelligent HLS tool must contain an expert system, which can give as much flexibility as possible to the designer during the design flow. The designer should be able to select the basic parameters of the design, either the maximum available silicon area, or the needed minimum speed. On the other hand, the design steps has to be hidden from the designer. The whole design management can be divided into two parts, High-Level Synthesis and Logic Synthesis. Both parts can be further broken down into several subparts. Any design flow starts from a representation. A microelectronic system is usually represented by a mathematical description, or a high level program language. All of these different representations considered at this stage are called Sehmioral Descriptions of the system. In this stage we deal with the design as a black box. We just deal with the inputs and the outputs and the connection hctween them The main goal of'the first step ( HLS I to rc'ceivc an etficient structure from the E3ehavioral Description. At this level several decisions have to be made without Ios~np any important freedom. For example the basic definitions of the 'building blocks' called Functional El'ements have to be degived. and the ratio between the duration time of the different operations emd the fastest elements ( single buffers ) has to be known. The technology independence does not onl:v mean that during the HLS technology dependent parameters are illegal. but it also indicates that the description of the output structure must be in a widespread HDL such as VHDL or Verilog. The next stage called Silicon Comprlarron provides a technology link, in which several methods anld CAD tools are available. We have been developing an HLS method and a software tool for pipelined data-flow structures called TSPD ( Time Scaled HLS for Pipelined Data-flow Structures ). In our method the Behavioral Description is represented by a Daro Flow Graph ( DFG ), which is the input structure. We iue still working on generating a VHDL description of the output structure, as a joint project .This method can handle operations with different arbitrap durations. This method has two basic parts: Scheduling : The scheduling began with a Behavioral Description ( DFG ), and the re","PeriodicalId":217615,"journal":{"name":"The Third Annual Atlantic Test Workshop","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129614155","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Test cost/coverage tradeoffs in complex telecommunication circuits","authors":"M. J. Aguado","doi":"10.1109/ATW.1994.747830","DOIUrl":"https://doi.org/10.1109/ATW.1994.747830","url":null,"abstract":"Cost and quality are crucial at any project development. These parameters are strongly interrelated and must be taken into account from the startting phases, of the development. However, in general, classical test tools we not flexible with these aspects. It is, they do not allow the designer to reduce test costs at the expense of a minimum loss in fault coverage. In this paper, the experience of Telefonica I+D concerning the mariagexnent of twt cost and quality factors will be praerrted. Emphasis will be applied to show the main problems that have appeared to generate the test of two high complexity telecommunication ASICS.","PeriodicalId":217615,"journal":{"name":"The Third Annual Atlantic Test Workshop","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121910799","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Near-optimal Test Sequencing Algorithms For Sequential Fault Diagnosisl","authors":"V. Raghavan, K. Pattipati","doi":"10.1109/ATW.1994.747834","DOIUrl":"https://doi.org/10.1109/ATW.1994.747834","url":null,"abstract":"In [1], optimal AN DIOR, graph search algorithms were developed to analyze the testability of a systeln design and to determine an optimal sequence of tests for the trouble-shooting of hierarchical systems. However, NP-hardness of the test sequencing problem makes the computation of optimal testseq{lence impractical for even moderate-sized problems. Hence, there is a need for near-optimal test sequencing algorithms that provide a trade-off between optimality and computational complexity. Consequently, we have developed three classes of nearoptimal algorithms: multi-step information heuristic, hybrid breadth-depth search, and rninimax heuristic. These algorithms compute fault isolation strategies with significantly lower computational requirements than the optimal A0\" algorithm and have enabled us to solve testability analysis problems with as many as 50,000 failure sources and 45,000 test points. In acdition, our test-sequencing algorithms handle precedence constraints on tests, overlapping setup operations for tests, rectification/replacement of modules, and fault isolation to any desired level of the system hierarchy. The above suite of test-sequencing algorithms were extended to handle the case of imperfect tests, where in missed detections and false alarms add another dimension of uncertainty to the testing process .","PeriodicalId":217615,"journal":{"name":"The Third Annual Atlantic Test Workshop","volume":"220 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133772921","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Acquisition And Analysis Of Decision Logic From Data","authors":"W. Ziarko, Ning Shan","doi":"10.1109/ATW.1994.747829","DOIUrl":"https://doi.org/10.1109/ATW.1994.747829","url":null,"abstract":"The paper discusses a methodology for derivation and analysis of decision algorithms from sensor data representing system states and operator actions. The methodology is based on the mathematical model of rough sets, The end result of the application of this methodology is a set of simple control rules connecting sensor readings with control decisions.","PeriodicalId":217615,"journal":{"name":"The Third Annual Atlantic Test Workshop","volume":"13 8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115844093","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Using VHDL for Link to Synthesis Tools","authors":"M. Belhadj","doi":"10.1109/ATW.1994.747844","DOIUrl":"https://doi.org/10.1109/ATW.1994.747844","url":null,"abstract":"This paper presents the work done to use industry and academic synthesis tools for the hardware-software codesign of reactive systems. It emphhizes the hardware synthesis and design part by linking SIGNAL and VHDL. The SIGNAL language is used for system specification and VHDL for the link to synthesis tools. To permit a maximum of flexibility, different strategies for linking are described.","PeriodicalId":217615,"journal":{"name":"The Third Annual Atlantic Test Workshop","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116812734","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}