使用VHDL链接到合成工具

The Third Annual Atlantic Test Workshop Pub Date : 1994-06-02 DOI:10.1109/ATW.1994.747844

M. Belhadj

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引用次数: 9

摘要

本文介绍了利用工业和学术合成工具进行反应系统硬件软件协同设计的工作。重点介绍了将SIGNAL与VHDL相结合的硬件综合与设计部分。SIGNAL语言用于系统规范，VHDL用于链接到合成工具。为了保证最大的灵活性，本文描述了不同的链接策略。

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Using VHDL for Link to Synthesis Tools

This paper presents the work done to use industry and academic synthesis tools for the hardware-software codesign of reactive systems. It emphhizes the hardware synthesis and design part by linking SIGNAL and VHDL. The SIGNAL language is used for system specification and VHDL for the link to synthesis tools. To permit a maximum of flexibility, different strategies for linking are described.

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The Third Annual Atlantic Test Workshop

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