Tme scaled high-level synthesis for pipelined data-flow structures

Abstract

Since integrated circle fabrication technology has reached the level of the million transistors. it has became more urgent to introduce new approaches of system level synthesis. In parallei that the set of the available basic elements are becoming more complex. as the processors have been widely applied. The High-Level Synthesis ( FILS ) provides a direction these problems can be handled with. A desirable feature of a design process using HLS is to minirnize its dependence on technology. The nature of the design tools has changed from simple assistance during the design flow, to sophisticated knowledge source, such as providing the designer with information about important tradeoffs determined by the application. .An intelligent HLS tool must contain an expert system, which can give as much flexibility as possible to the designer during the design flow. The designer should be able to select the basic parameters of the design, either the maximum available silicon area, or the needed minimum speed. On the other hand, the design steps has to be hidden from the designer. The whole design management can be divided into two parts, High-Level Synthesis and Logic Synthesis. Both parts can be further broken down into several subparts. Any design flow starts from a representation. A microelectronic system is usually represented by a mathematical description, or a high level program language. All of these different representations considered at this stage are called Sehmioral Descriptions of the system. In this stage we deal with the design as a black box. We just deal with the inputs and the outputs and the connection hctween them The main goal of'the first step ( HLS I \ to rc'ceivc an etficient structure from the E3ehavioral Description. At this level several decisions have to be made without Ios~np any important freedom. For example the basic definitions of the 'building blocks' called Functional El'ements have to be degived. and the ratio between the duration time of the different operations emd the fastest elements ( single buffers ) has to be known. The technology independence does not onl:v mean that during the HLS technology dependent parameters are illegal. but it also indicates that the description of the output structure must be in a widespread HDL such as VHDL or Verilog. The next stage called Silicon Comprlarron provides a technology link, in which several methods anld CAD tools are available. We have been developing an HLS method and a software tool for pipelined data-flow structures called TSPD ( Time Scaled HLS for Pipelined Data-flow Structures ). In our method the Behavioral Description is represented by a Daro Flow Graph ( DFG ), which is the input structure. We iue still working on generating a VHDL description of the output structure, as a joint project .This method can handle operations with different arbitrap durations. This method has two basic parts: Scheduling : The scheduling began with a Behavioral Description ( DFG ), and the result is a smartly scheduled structure. It works by inserting extra buffers, and by multiple operations. Allocation : The allocation method is based on a compatibility relation problem. The aim of this method is to find the least number of necessary processors needed to realize the design.