2013 IEEE 15th Electronics Packaging Technology Conference (EPTC 2013)最新文献

{"title":"Thermal cycling reliability assessment and enhancement of embedded wafer level LGA packages for power applications","authors":"Yiyi Ma, K. Goh, Xueren Zhang, Yonggang Jin","doi":"10.1109/EPTC.2013.6745792","DOIUrl":"https://doi.org/10.1109/EPTC.2013.6745792","url":null,"abstract":"With great feasibility and flexibility for growing I/Os, multi-chips and system integration, the emerging fan-out embedded Wafer Level BGA (eWLB) technology is regarded as a much more favorable packaging solution compared with its traditional counterparts, i.e. fan-in WLP or BGA technology. The relentless trend of ever increasing integrated circuit chip functionality and decreasing chip dimensions for miniaturization of products have led to less chip real estate and intense heat dissipation. While eWLB technology has well addressed the routing problems associated with the former, its intrinsic ineffectiveness of reducing the spreading thermal resistance of the shrunk die has limited its application to low power devices. As a result, Quad Flat No-Lead (QFN) is often a packaging technology of choice for those applications as QFN is a lead frame based package which offers thermal and electrical enhancement with its exposed die pad on the bottom of the package surface. The exposed die pad not only provides an efficient heat path to the PCB, but also enables stable grounding with electrical connection through a conductive die attach material. To bridge the gap between the eWLB and QFN concept so that both of their advantages can be retained, STMicroelectronics has recently come up with a QFN-like eWLB package known as embedded wafer level LGA (eWLL) with low profile, high pin count and excellent thermal and electrical performance. This paper initially investigated the solder joint reliability of the eWLL packages under board level Accelerated Thermal Cycling (ATC) test through Finite Element Analysis (FEA). Experiments were then carried out to assess the accuracy of the FEA model. It was found that the predictions made by the FEA simulation correlated very well with the actual test results. The validated FEA model was then extended to study the effect of a wide range of design variables on the board level reliability of the eWLL packages. The results of the numerical analysis are compared and discussed in details.","PeriodicalId":210691,"journal":{"name":"2013 IEEE 15th Electronics Packaging Technology Conference (EPTC 2013)","volume":"501 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125879744","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Transient liquid phase (TLP) bonding using Sn/Ag multilayers for high temperature applications","authors":"N. Nobeen, R. Imade, B. Lee, Eric Jian Rong Phua, C. Wong, C. Gan, Zhong Chen","doi":"10.1109/EPTC.2013.6745799","DOIUrl":"https://doi.org/10.1109/EPTC.2013.6745799","url":null,"abstract":"With the growing demand for electronic devices operating in harsh conditions, the interconnect technology for packaging these devices remains an important area of focus to ensure reliable and stable functioning capabilities. Because these devices may experience temperatures that are higher than those encountered by consumer electronic products (e.g. for down-well tools in oil and gas drilling up to 200°C, automotive application up to 400°C), the die attach material has to withstand high temperatures generated during the device functioning, as well as external conditions without affecting the device performance. Conventional solders used in consumer electronic products have melting points lower than the maximum operating temperatures of harsh environment applications, and they are thus not appropriate for use. In contrast, metallurgical systems that can be bonded using the transient liquid phase (TLP) bonding process is a promising solution for high temperature electronic devices due to the following benefits, namely: (1) high quality bond can be formed, (2) a bond can be formed at a temperature much lower than the melting point of the resulting joint. In this paper, the feasibility to bond silver-tin (Ag-Sn) system using the TLP bonding process and use it as a die attach solution for high temperature electronic systems is reported. The advantages Ag-Sn system provides are low bonding temperature, low cost, high de-bonding temperature, and it is also one of the fast inter-diffusion couples. The influence of bonding parameters, such as bonding temperature, bonding force, on the quality of the TLP bond is discussed in order to develop a Ag-rich bond. The joints developed were inspected using X-ray and SEM/EDX, coupled with shear tests performed at room temperature to determine the mechanical strength of the joint. From the bonding studies, a Ag-Sn TLP bond was successfully developed. No occurrence of voids was found in the bonded area, and from the SEM/EDX analysis the joint was comprised of Ag and Ag3Sn intermetallic only, thereby achieving the desired Ag-rich joint. On the other hand, from the mechanical characterisation tests, the shear strength of the Ag-Sn bonded samples was observed to be higher than the minimum strength requirement for high temperature applications. The shear strength also increased with bonding pressure and temperature.","PeriodicalId":210691,"journal":{"name":"2013 IEEE 15th Electronics Packaging Technology Conference (EPTC 2013)","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125127107","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Low impedance characterization of power delivery network on substrate level for high speed digital applications","authors":"Wui-Weng Wong, Suat-Mooi Low, B. Beker","doi":"10.1109/EPTC.2013.6745816","DOIUrl":"https://doi.org/10.1109/EPTC.2013.6745816","url":null,"abstract":"This paper describes an effective characterization technique developed for low impedance extraction of the power delivery network (PDN) in today's high-speed digital applications. Sub-milliohm impedances across almost DC to tens of MHz can be measured accurately on a microprocessor substrate with cutting edge design of the decoupling scheme. Compared to the conventional solutions of getting transfer-impedance obtained by 2-port vector network analyzer (VNA) measurement data, gain-phase test port provided by commercial RF network analyzer is utilized due to its ground loop error elimination architecture. An exercise to optimize locations of excitation probing point and receiving probing point is shown to minimize potential spurious coupling through via loops in a typical flip chip substrate. The accuracy of this low impedance characterization method is further demonstrated by first order modeling of the equivalent series resistance (ESR) & equivalent series inductance (ESL) of a PDN with surface-mounted and embedded discrete chip capacitors.","PeriodicalId":210691,"journal":{"name":"2013 IEEE 15th Electronics Packaging Technology Conference (EPTC 2013)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124235809","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Challenges and approaches of ultra-fine pitch Cu pillar assembly on organic substrate using wafer level underfill","authors":"S. Lim, L. Siow, T. Chai, V. S. Rao, K. Takeda, T. Enami, C. G. Koh, XiangFeng Wang, Hongqi Sun, T. Ando","doi":"10.1109/EPTC.2013.6745778","DOIUrl":"https://doi.org/10.1109/EPTC.2013.6745778","url":null,"abstract":"The use of flip-chip technology in packaging interconnects is becoming more important due to its better electrical performance, smaller form factor packages, and higher interconnect density than wire bonded packages. Flip-chip soldering has been the mainstream flip-chip technology. However, the move towards fine pitch Cu pillar flip chip packaging with fine pad bond pitch has driven the investigation of Sn plated bumps on Cu pillar encapsulated with wafer level underfill as a potential alternative [1]. As the pitch of the electrical interconnections decreases and chip size increases, it is more difficult to develop high through-put processes using conventional capillary flow underfills. A WLUF process eliminates the time required to dispense conventional underfill to every chip and for capillary flow [2]. Fillers are used in underfill materials to decrease the coefficient of thermal expansion (CTE) which has the effect of reducing package stresses, and helping to achieve better reliability performance. However, in the case of WLUF with high filler content, it is very challenging to achieve 100% electrically and metallurgically good Pb-free solder joints and void-free underfill as the epoxy based WLUF can cure early, below the Pb-free solder melting temperature, and become trapped between flip chip bumps and substrate solder pads. Also, the high process temperature of Pb-free solder can cause a large amount of voids to form within the WLUF material during the solder joining cycle [3-4]. In the paper, a WLNCF with 40% fillers was laminated onto 8 inch wafer containing Cu pillar post with Sn solder bumps by spin coating. The wafer was diced into chips. A chip was aligned and joined to a substrate with an optimized heating and cooling cycle. The effects of the bonding parameters and bonding temperature profile on the fine pitch flip chip assembly on solder wetting, solder joint shape and WLNCF voids are addressed in this paper. The main challenge for the fine pitch flip chip assembly was to assemble a fine pitch Cu pillar assembly onto an organic substrate while ensuring good solder wetting, good bonding placement accuracy, minimum solder joint voids, good fillet coverage and no wafer level underfill trapped between the solder and substrate bond pad after thermocompression bonding. In addition, wafer level underfill lamination uniformity and voids after lamination and B-stage cure were inspected. Wafer dicing evaluation was also performed to ensure no debris or particles adhering to the WL-NCF during dicing. No peeling or delamination of the WL-NCF was observed after dicing. The impact of these various factors on the stacked die assembly is discussed in this paper.","PeriodicalId":210691,"journal":{"name":"2013 IEEE 15th Electronics Packaging Technology Conference (EPTC 2013)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124252136","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Die attach delamination resolution for exposed pad LQFP with large package size","authors":"Khoo Ly Hoon, Lau Teck Beng, Au Yin Kheng","doi":"10.1109/EPTC.2013.6745780","DOIUrl":"https://doi.org/10.1109/EPTC.2013.6745780","url":null,"abstract":"Integrated circuit (IC) package delamination defect refers to interface adhesion failures between either die to die attach material, die attach material to die paddle interface, or mold compound material to die paddle interface delamination, all of which are equally critical, in particular, for exposed pad Low Profile Quad Flat Packages (LQFPs) for large package sizes. Most of the devices with minor delamination are not easily detectable during device testing, but may potentially cause functional failure in certain applications in the field, especially after external mechanical stresses have been applied. There is no option of reworking these devices, and the IC manufacturer may suffer heavy cost impacts if the suspected defective units have to be recalled as customer return. Thus, the semiconductor industry is aggressively striving to improve the delamination performance in IC packaging. However, to date, this task is complicated and difficult as the defective failure is highly dependent on the compatibility of the material characteristic that may influence the entire IC package system under certain stress level, both mechanical and thermal stresses. In the first part of this paper, a detailed process mapping is established to determine the possible delamination root causes by performing a fish bone diagram mapping on the cause and effect. The different suspected causes include, among others, contribution from contamination factors on the die back and lead frame surfaces. In addition, a preliminary check on the existing cure profile and recommended profile from die attach material supplier was studied to enhance the adhesion between die back to die attach material interfaces. A process characterization is done to optimize the die attach cure profile recipe to enable zero voids formation, and at the same time, achieve good die pull strength value. In the second portion of this paper, a detailed die stress modeling was performed to examine various suspected high stress point in the IC package for better understanding in terms of overall package mechanical behavior. The critical factors such as the die edge to flag edge clearance, different bond line thickness (BLT), different die thickness and different fillet height phenomenon were analyzed. Finally, a detailed design of experiment (DOE) was generated based on the combination of the significant factors from the die stress modeling and also, from the material characteristic result analysis. The robustness of the package interface was then tested based on the reliability performance up to the required number of temperature cycling tests. The proper selection of leadframe die paddle size, epoxy material and epoxy cure profile was found to be able to successfully passed temperature cycling at -50°C to 150°C up to 2000 cycles.","PeriodicalId":210691,"journal":{"name":"2013 IEEE 15th Electronics Packaging Technology Conference (EPTC 2013)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123644790","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Study on reliability of ultrathin device embedded in organic substrate under drop impact loading using stresses monitor and simulation","authors":"Zhaohui Chen, Xiaowu Zhang","doi":"10.1109/EPTC.2013.6745831","DOIUrl":"https://doi.org/10.1109/EPTC.2013.6745831","url":null,"abstract":"Reliability of the embedded ultrathin device in the organic substrate packaging is one of major concerns during its applications. In this paper, drop impact tests were conducted to the embedded ultrathin stress sensor chip in the organic substrate. Stresses were monitored with the embedded stress sensor chip based on silicon piezoresistive effects. Dynamic explicit finite element model with the input-G method was built up to investigate the stress and strain behaviors of the embedded chip and solder bump. The drop impact simulation model was validated by the experimental stresses monitoring results. It indicated that the discrepancy of the normal stress σ11 at the center of embedded stress sensor chip from experimental and numerical simulation results is within 10%. Based on the validated model, the effects of material properties and structural parameters on the stress and strain responses were studied by the numerical simulation. The maximum normal stress σ11 at the embedded sensor chip and the peeling stress σ33 of the solder bump were selected as the indexes for the comparisons and optimizations. The experimental and numerical simulation efforts can provide design guidelines for the embedded ultrathin chip in the organic substrate packaging.","PeriodicalId":210691,"journal":{"name":"2013 IEEE 15th Electronics Packaging Technology Conference (EPTC 2013)","volume":"105 12S1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121588343","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Chip on board (COB) versus board on chip (BOC) memory packages","authors":"Chong Chin Hui, Wang Ai Chie","doi":"10.1109/EPTC.2013.6745817","DOIUrl":"https://doi.org/10.1109/EPTC.2013.6745817","url":null,"abstract":"Due to intense competition in the consumer electronics landscape, especially in the mobile communication products sector, new memory products (both DRAM and NAND Flash) must meet higher speed requirements, be packaged in smaller form factors, and achieve higher densities. Therefore, the most common package types-board on chip (BOC) for DRAM and chip on board (COB) for NAND Flash-must be analyzed to determine whether they can meet current and future packaging challenges. The components of COB and BOC substrates that are being studied are traces, bond fingers, the number of metal layers, and vias. Based on the trends of these substrate components, future substrates will be required to have at least two metal layers (BOC in particular), utilize narrower bond finger pitches, be thinner than 0.13mm and have vias with via land/drill hole sizes of less than 220μm/100μm. Further work must be performed to determine the minimum required trace width value based on the existing warpage specifications as well as the minimum required bond finger pitch as a function of die length.","PeriodicalId":210691,"journal":{"name":"2013 IEEE 15th Electronics Packaging Technology Conference (EPTC 2013)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122067917","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Developing underfill process in screening of no-flow underfill and wafer-applied underfill materials for 3D stacking","authors":"K. Rebibis, G. Capuz, R. Daily, C. Gerets, F. Duval, W. Teng, H. Struyf, R. A. Miller, G. Beyer, E. Beyne, B. Swinnen","doi":"10.1109/EPTC.2013.6745697","DOIUrl":"https://doi.org/10.1109/EPTC.2013.6745697","url":null,"abstract":"The demands and challenges in pushing the limits of Moore's Law made the 3D IC stacking radiate the pressure for MPTs (materials, processes and tools) in keeping up with the technology. The 3D IC architecture design built around the TSVs, micro-bumps and thinned wafers/dies is the center of the show, of which the MPTs must conform and be viable to be part of the supporting cast. Underfilling's main objectives is to provide the mechanical stability for micro-bumps and prevents moisture between the resulting gap between dies before the 3D stack is sent for packaging. With several complexities in 3D stacking had to be considered and addressed in applying the underfill materials. Complexities such as the stacking options Die-to-Die (D2D) or Die-to-Wafer (D2W), the thicknesses of the dies to be stacked (~50 um die thickness), the thermo-compression bonding parameters to be used and the behavior of the underfill materials to the different process parameters had to considered during the characterization process of underfills.","PeriodicalId":210691,"journal":{"name":"2013 IEEE 15th Electronics Packaging Technology Conference (EPTC 2013)","volume":"330 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122138430","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Thermal management of hotspots using upstream laminar micro-jet impinging array","authors":"Yong Han, Yong Jiun Lee, B. L. Lau, Xiaowu Zhang, Y. Leong, K. F. Choo, P. Chan","doi":"10.1109/EPTC.2013.6745689","DOIUrl":"https://doi.org/10.1109/EPTC.2013.6745689","url":null,"abstract":"The problem of heat removal is likely to become more severe due to the presence of hotspots in the integrated circuit chip. The heat dissipation capability of the upstream laminar micro-jet impinging array is investigated for hotspot cooling. Micro-jet impingement array cooling is an effective method of using liquids to cool electronics where high convective heat transfer rates are required. Several simulations have been implemented on the thermal structure of 4 tiny inline-aligned hotspots to evaluate the heat dissipation capability of the laminar micro-jet impinging array. The effects of the jet diameter, jet pitch and jet-to-wall distance on the Nusselt number, heat convection coefficient, Reynolds number and thermal resistance are studied. The limit of the dissipated heat fluxes of the considered thermal structure are evaluated for the hotspots of different sizes.","PeriodicalId":210691,"journal":{"name":"2013 IEEE 15th Electronics Packaging Technology Conference (EPTC 2013)","volume":"72 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123263051","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"High density chip-to-wafer integration using self-assembly: On the performances of directly interconnected structures made by direct copper/oxyde bonding","authors":"S. Mermoz, L. Sanchez, L. Di Cioccio, J. Berthier, E. Deloffre, P. Coudrain, C. Fretigny","doi":"10.1109/EPTC.2013.6745705","DOIUrl":"https://doi.org/10.1109/EPTC.2013.6745705","url":null,"abstract":"We present here our latest results on chips-to-wafer 3D structures obtained with the self-assembly technology adapted on copper/oxide patterned surfaces. Technological integration, bonding quality and alignment accuracy are presented and the electrical contact of the interconnection is evaluated. High speed high alignment accuracy chip-to-wafer hybridation technique is mandatory for 3D technology. Chip-to-wafer self-assembly processes coupled to direct bonding hybridization is on the merge to breakthrough this issue. In a previous work [1], we demonstrated submicronic alignment accuracy and a 90% self-assembly process yield with this technique. In this paper, we discuss on interconnect electrical characterization of self-assembled chips compared to chips assembled with conventional Pick and Place method. Interface resistance is evaluated on daisy chain and Kelvin structures. The quantification of the alignment is measured thanks to vernier and is in the range of a few hundred nanometers. The liquid drop impact on assembled structure, considering the different aspects (bonding quality, Cu-chemical oxidation, mechanical chip level bow and electrical resistance) is discussed.","PeriodicalId":210691,"journal":{"name":"2013 IEEE 15th Electronics Packaging Technology Conference (EPTC 2013)","volume":"54 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131893710","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}