2013 IEEE 15th Electronics Packaging Technology Conference (EPTC 2013)最新文献

{"title":"An advanced MEMS sensor packaging concept for use in harsh environments","authors":"J. von Berg, C. Cavalloni, B. Mukhopadhyay, P. Mackowiak, O. Ehrmann, K. Lang, H. Ngo","doi":"10.1109/EPTC.2013.6745692","DOIUrl":"https://doi.org/10.1109/EPTC.2013.6745692","url":null,"abstract":"The presented package for harsh environment fulfills the demands to withstand high temperatures of 400°C, aggressive media and pressures up to 50 bar as it uses a steel membrane with an indenter which pushed on the center-boss structure of the sensor. Thus no transmitting media like oil is needed. The SOI sensor chip consists of a beam with an integrated center-boss which was realized using KOH structuring and DRIE (Deep Reactive Ion Etching/Bosch Process). The SOI technology has the distinct advantage that the piezo-resistors are not isolated by a pn junction from the dielectric substrate but by a buried oxide layer. In combination with a high temperature metallization, the SOI-chip is able to withstand the demands of high temperatures. The high temperature metallization consists of a sputtered Ti/TiWN layer that has been exposed to special RTA (rapid thermal annealing) process. Afterwards a TiWN and an Au layer are sputtered followed by an Au electro plating process. The chip has four piezoresistors that are arranged in pairs of longitudinal and transversal resistors which are compressed when pressure is applied. The four resistors are connected via conductors to a Wheatstone bridge. The sensor chip has a beam thickness of 25 μm and the center-boss has an area of lmm × lmm. The beam has a natural frequency of approx. 20 kHz. The sensor chip is mounted using Flip Chip technology to avoid a wire bond technology. It is mounted on a glass feed through on which stud bumps are located and conducted using thermo-compression process. The pressure range is set by varying the steel membrane thickness. This concept has a mayor advantage that the sensor chip can be used for various pressure ranges. The thickness of the steel membrane is chosen adopted to the pressure range, so that the deflection of the sensor beam is 12μm when the maximum pressure is applied.","PeriodicalId":210691,"journal":{"name":"2013 IEEE 15th Electronics Packaging Technology Conference (EPTC 2013)","volume":"164 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115275444","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Study of power integrity challenges in high-speed I/O design using power rails merging scheme","authors":"Li Wern Chew, Paik Wen Ong","doi":"10.1109/EPTC.2013.6745695","DOIUrl":"https://doi.org/10.1109/EPTC.2013.6745695","url":null,"abstract":"Modern electronic devices such as tablets and smartphones are getting more powerful and efficient. The demand in feature sets, functionality and usability increase exponentially and this has posed a greater challenge to the design of a power distribution network (PDN). Power rails merging is a popular option adopted today in a PDN design as the provision of numerous power rails is no longer feasible due to form factor limitation and cost constraint. In this paper, a study of power integrity challenges in a high-speed input/output design using power rails merging scheme is presented. Despite having all the advantages such as pin count reduction, decoupling capacitors sharing, lower impedance and cost saving, power rails merging can however, introduce coupling noise to the system. In view of this, a PDN design with power rails merging that fulfills design recommendations and specifications such as noise target, power well placement, voltage supply values as well as power supply quadrant assignment is extremely important.","PeriodicalId":210691,"journal":{"name":"2013 IEEE 15th Electronics Packaging Technology Conference (EPTC 2013)","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115632935","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Development of bonding process for high density fine pitch micro bump interconnections with wafer level underfill for 3D applications","authors":"V. S. Rao, S. Chong, C. Zhaohui, J. Aw, Eva Wai Leong Ching, Hwang Gilho, D. M. Fernandez","doi":"10.1109/EPTC.2013.6745779","DOIUrl":"https://doi.org/10.1109/EPTC.2013.6745779","url":null,"abstract":"Realization of 3D IC packaging is mainly depends on the success of fine pitch micro bump bonding process for thin chips stacking and reliability of micro bump interconnections between stacked chips. The uniformity of micro bumps is the critical requirement to achieve good micro bump bonding, and the chip warpage during bonding and underfilling of micro gaps between stacked chips is key challenge in 3D IC packaging. In this work, The FEM modeling and simulations has been carried out to understand the effect of the package parametric on chip warpage and results revealed that chip thickness and substrate thickness has significant effect on chip warpage. The warpage of the test chip with TSVs is lower when compared to test vehicle without TSVs. The fabrication process has been optimized to achieve uniform high density fine pitch micro bumps of 10 μm diameter at 20 μm pitch. Flip chip bonding processes for 20 μm pitch micro bumps with and without pre-applied wafer level underfill material are optimized using conventional reflow and thermal compression bonding (TCB) respectively. Capillary underfill process is also optimized for micro gaps of less than 20 μm and achieved void free underfilling. Thermal compression bonding temperature and force profiles are optimized for micro bumps with pre-applied wafer level underfill material, and achieved good micro bump joints with void free underfilling. Cross-sectional analysis revealed good micro bump joints with and without pre-applied underfill materials and CSAM analysis revealed void free underfilling is feasible using capillary underfilling as well as TCB with pre-applied wafer level underfill. Finally, this paper demonstrated bonding process for high density fine pitch micro bumps for thin large chips stacking which required for 3D IC packaging application.","PeriodicalId":210691,"journal":{"name":"2013 IEEE 15th Electronics Packaging Technology Conference (EPTC 2013)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123084538","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Mechanical properties investigation of graphene coated with Ni","authors":"Youkai Chen, F. Zhu, Kai Tang, Ying Li, H. Liao, Xiahui Chen, Sheng Liu","doi":"10.1109/EPTC.2013.6745822","DOIUrl":"https://doi.org/10.1109/EPTC.2013.6745822","url":null,"abstract":"This work investigated mechanical behaviors of graphene and graphene coated with Ni (graphene-Ni) by using molecular dynamics (MD) method. By performing the MD simulation for uniaxial tension simulations, it could be noted that the graphene is more unstable than graphene-Ni at the same temperature from the result of molecular dynamics simulation for two models. It is observed that nickel atoms coated on the surface of graphene can increase the critical stress of graphene. As well, the young's modulus of graphene is much lower than graphene-Ni. Two different models of graphene and grapheme-Ni were analyzed at 200K, 300K, 500K, 700K and 1000K respectively in order to understand the effect of temperature.","PeriodicalId":210691,"journal":{"name":"2013 IEEE 15th Electronics Packaging Technology Conference (EPTC 2013)","volume":"68 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115757579","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Effect of IMC growth on thermal cycling reliability of micro solder bumps","authors":"Haiyan Liu, Cheng Xu, Xiaoyang Liu, Daquan Yu, Fengwei Dai, Yuan Lu, D. Shangguan","doi":"10.1109/EPTC.2013.6745839","DOIUrl":"https://doi.org/10.1109/EPTC.2013.6745839","url":null,"abstract":"In this study, thermal cycling reliability tests and analysis for micro solder bump in 2.5D packaging were conducted. Finite element analysis modeling of micro bump with different intermetallic compound (IMC) thickness was developed to model the effect of IMC layer on fatigue behavior of micro bumps. It was found that stress in solder increased notably when the IMC layer is taken into consideration, and increased slightly as further increase in the IMC thickness. The thermal mechanical stress in IMC layer was also studied to assess the reliability of IMC integration. It was found that the stress decreased sharply with the increase of IMC thickness; when all the solder transformed into IMC, the thermal mechanical stress decreased to only 20% of the stress in 1μm IMC. Failure mode after thermal cycling tests was analyzed by cross section morphology. Cohesive cracks in the solder took place at the interface of tin solder and IMC layer, and heavier damage was found in bumps with thicker IMC thickness, which agreed well with the FEA results.","PeriodicalId":210691,"journal":{"name":"2013 IEEE 15th Electronics Packaging Technology Conference (EPTC 2013)","volume":"82 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117263862","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Effect of processing on the microstructure and fracture of solder microbumps in 3D packages","authors":"Z. Chen, B. Talebanpour, Z. Huang, P. Kumar, I. Dutta","doi":"10.1109/EPTC.2013.6745777","DOIUrl":"https://doi.org/10.1109/EPTC.2013.6745777","url":null,"abstract":"Solder microbumps are receiving increasing interest due to their application in 3D-packages which facilitate the miniaturization of electronic devices. The reliability of microbumps during a drop event is of great concern because of their large proportion of intermetallic compounds (IMCs) which are of brittle nature. In this paper, the growth kinetics of IMCs in solder joints were analyzed. Compact mixed mode (CMM) samples with an adhesive solder joint between Cu substrates were used to simulate microbumps for evaluation of the fracture properties. The effect of IMC proportion, strain rate, and mode mixity on fracture toughness were investigated. It was found that with increasing aging, the IMC proportion increased, leading to lower fracture toughness and more brittle fracture. In addition, the fracture toughness decreased with increasing strain rate and mode mixity.","PeriodicalId":210691,"journal":{"name":"2013 IEEE 15th Electronics Packaging Technology Conference (EPTC 2013)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127176315","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Study on silver sintered die attach material with different metal surfaces for high temperature and high pressure (300°c/30kpsi) applications","authors":"L. Wai, W. Seit, E. Rong, M. Ding, V. S. Rao, Daniel Rhee Minwoo","doi":"10.1109/EPTC.2013.6745738","DOIUrl":"https://doi.org/10.1109/EPTC.2013.6745738","url":null,"abstract":"In this study, Silver sintering material is being evaluated on different metal surfaces for high temperature storage and high temperature plus high pressure test up to 300°C/30kpsi. Three different type of Alumina based ceramic substrates (gold, silver and copper metal finishes) are used as test vehicle in this evaluation. Die attach material and process quality has been evaluated in terms of die shear strength before and after high temperature storage for gold and silver surfaces, further study is the evaluation for the combined test with high temperature and high pressure (HTHP) for plasma treated metal surfaces (silver, gold and copper) and failure mode analysis. Silver-filled epoxy and high temperature epoxy materials are also used as references to make comparison with sintered materials at high temperature storage. After high temperature (300°C) storage test for 500 hours, shear strength of silver surface samples is increased from average shear strength of 17.96N/mm2 to 25.97N/mm2. However, shear strength of gold surface finished (ENEPIG) samples are decreased drastically from average shear strength of 14.78N/mm2 to 0.30N/mm2. A porous layer is observed at the interfaces near the dense Au/Ag alloy between Ni/Pd/Au finished surface and Ag sintering layer where the interfacial failure mode is happened. High temperature (300°C) and high pressure (30kpsi) storage test samples for 500 hours shows relatively higher shear strength for both silver surface and ENEPIG surface while degradation happened on the bare copper surface. After combined HPHT test (300°C/30kpsi/500hours), gold layer in ENEPIG surface is diffused into palladium and nickel layers without creating a porous layer near the Au/Ag alloy and the exhibits good shear strength results which is significantly different behavior from the high temperature storage without pressure. SEM and EDX are used to analyze the cross-sectioned layers after HPHT aging tests. Silver sintering on copper surface shows the lowest shear strength among Ag, Au and Cu substrates. Au substrates has an average shear strength of >20N/mm2, which is higher than Ag substrate which has an average shear strength of >10.9N/mm2.","PeriodicalId":210691,"journal":{"name":"2013 IEEE 15th Electronics Packaging Technology Conference (EPTC 2013)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127488198","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Performance enhancement of Au-Ge eutectic alloys for high-temperature electronics","authors":"V. Chidambaram, E. Rong, Gan Chee Lip, M. Rhee","doi":"10.1109/EPTC.2013.6745713","DOIUrl":"https://doi.org/10.1109/EPTC.2013.6745713","url":null,"abstract":"Au-Ge eutectic has been used as a high temperature electronics interconnection material up to 250°C due to its favorable characteristics. However, both nano-indentation and shear testing, confirmed the loss of strength of the Au-Ge eutectic at a high temperature of 300°C due to the growth of the (Ge) phase. This coarsening has also resulted in the weakening of the (Au) phase due to the deterioration of the precipitation hardening of the (Au) matrix by the (Ge) dispersed phase. In this paper, various techniques for averting the coarsening of the (Ge) phase have been explored. It has been determined that Sn can dissolve in the Au-Ge and segregate in the (Ge) phase, resulting in restraining the coarsening of the (Ge) phase. The composition of the ternary Au-Ge-Sn alloy has been designed by taking into account; the compliance with the solidification criterion and precipitation of phases in the bulk solder. It has been ensured that no brittle intermetallic compounds (IMCs) precipitate in the matrix of the Au-Ge eutectic bulk solder, as a result of micro-alloying with Sn.","PeriodicalId":210691,"journal":{"name":"2013 IEEE 15th Electronics Packaging Technology Conference (EPTC 2013)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126122823","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"An innovative and low cost Bi-layer method for temporary bonding","authors":"J. Burggraf, H. Wiesbauer, Julian Bravin, T. Uhrmann, H. Meynen, Y. Civale, R. John, Sheng Wang, Peng-Fei Fu, C. Yeakle","doi":"10.1109/EPTC.2013.6745685","DOIUrl":"https://doi.org/10.1109/EPTC.2013.6745685","url":null,"abstract":"The purpose of this work was to demonstrate the compatibility of Dow Corning's temporary bonding solution with EVG's 850XT universal temporary bonding and debonding platform. The proposed process made use of well-known processing steps and processing modules like spin coating. The process consisted of a release layer (Dow Corning® WL-3001 Bonding Release) and an adhesive layer (Dow Corning® WL-4050 or WL-4030 Bonding Adhesive) using an EVG® 850TB - 300 mm XT frame. Both layers of material were applied by spin coating on the device wafer side. In the frame of this study, silicon carriers were used. Bonding was performed under vacuum at room temperature. A post bonding bake step was applied using a hotplate. After subsequent backside processing steps, the room temperature debonding was performed.","PeriodicalId":210691,"journal":{"name":"2013 IEEE 15th Electronics Packaging Technology Conference (EPTC 2013)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123286026","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A robust development for QFP Cu wire necking prevention in automotive grade 0 temperature cycle reliability","authors":"C. Tai","doi":"10.1109/EPTC.2013.6745734","DOIUrl":"https://doi.org/10.1109/EPTC.2013.6745734","url":null,"abstract":"Cu wire is increasing in usage in semiconductors due to continuous package cost reduction. Raising bar for reliability requirements, especially customers in automotive industry, has posted numerous challenges for Cu wire in meeting stringent quality requirements. This study is triggered by customer to development Grade 0 temperature cycles (TC) reliability with lower cost. Current package is running with Au wire Grade 1 TC reliability. In order to have better profit margin, internal decision was targeted on bare Cu wire to run with Grade 0 TC reliability at the initial stage. The focus of this paper is development of Cu wire for QFP robust wire necking prevention in Grade 0 temperature cycling (TC) reliability. Wire necking is one the major reliability concern in Grade 0 TC. The first failure of Grade 0 TC is observed with massive open failure after TC500X Grade 0 stress test. Further FA confirmed that wire is rapture due to wire necking. At the same time, the FA expert zooming into the each comer to quantify & classify the failure mode. The failure is localized at north/west of the wire bonded area this area is where the leadframe is not symmetry in design. Other area showed minor or no crack line no broken wire observed. In order to meet the Grade 0 TC, the investigation is streaming into 3 directions: First, process driven weaknesses for bare Cu wire. Second, comprehensive simulation was done in order to foster the development understanding and lastly, Cu wire material understanding. In process driven weaknesses, after series of wirebond & moulding process provocation, only two key indicators showed influence: vibration control during wirebond with different clamper design & symmetry leadframe design influence to stress distribution. Wirebond clamper with reduced vibration on leadfinger (spring loaded design) had significantly improved the zero hour on first bond with no micro line or surface dislocation. Despite also improve the second bond wedge peeling significantly. However, after TS 1000X, crack line is observed again on pin 86 & 92 (which is the bad corner). While in symmetry leadframe design, minor crack line is observed after TS 1000X. However, the bad comer effect was deleted as all location observed certain degree of minor crack line. At the same time, a comprehensive simulation with seven parameters & fifteen details items to be considered for further improvement. The simulation had also completed with priority on the key factors as die thickness, mould compound CTE & mould compound glass transition temperature (Tg). Thus, selected mould compound Tg & CTE did not showed positive contribution after TS1000X. The conclusion is then laid down to bare Cu wire intrinsic weaknesses lead to early failure. In term of Cu wire material understanding, based on in-house stress strength curve comparison between two type of bare Cu wire & 2 Type of Pd coated Cu wire, Pd coated wire exhibited some advantages over bare Cu wire: 1) Pd coated wire exh","PeriodicalId":210691,"journal":{"name":"2013 IEEE 15th Electronics Packaging Technology Conference (EPTC 2013)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122190093","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}