2013 IEEE 15th Electronics Packaging Technology Conference (EPTC 2013)最新文献

{"title":"Fault isolation with backside polish for trench Schottky diode","authors":"Norhazlina Ismail, Muhammad Hasif Nasaruddin, B. A. Rahim, Wan Sabeng Wan Adini, Mohd Rofei Mat Hussin","doi":"10.1109/EPTC.2013.6745806","DOIUrl":"https://doi.org/10.1109/EPTC.2013.6745806","url":null,"abstract":"Photon Emission Microscopy (PEM) is one of the well-known fault isolation tool used in most failure analysis lab. The tool works on a principle whereby light will be emitted from the electron-hole pair recombination and carrier excitation when there is junction breakdown. However, this light emission is very weak causing fault isolation impossible to be detected on front side of Schottky diode wafer which is covered with thick Aluminium metallization. Therefore, a backside polishing method is required to thin the bulk Silicon to allow optimum transmission and thus failure site localization. In this study, Schottky diode wafer which has failed low (early) junction breakdown was thin down from total thickness of 640um. Final thickness of 40um does reveal an emission but do not able to show the die pattern. Emission was detected using InGaAs camera (λ=900nm to 1600nm). Die pattern is needed to be seen from the backside to be able to locate the exact fault localization spot on the front side. Die were further thin down to final thickness of 30um of total thickness including metallization. This paper will reveal the steps taken to polish die backside which is done by using ASAP-1 Ultratec sample preparation tool. Results showed that after thinning bulk Silicon to 30um with mirror finishing, die pattern was clearly visible. Fault localization done using PHEMOS 1000 where emission spot observed and samples were continued with cross-sectioning analysis. Cross-sectional analysis using Dual Beam system showed that there is Aluminium metallization diffused into mesa and trench region. Aluminium migration into these regions will cause high leakage and lowe (early) junction breakdown failure on the trench Schottky diode.","PeriodicalId":210691,"journal":{"name":"2013 IEEE 15th Electronics Packaging Technology Conference (EPTC 2013)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123914868","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"The cost study of 300mm through silicon interposer (TSI) with BEOL interconnect","authors":"H. Li, G. Katti, Liang Ding, S. Bhattacharya, G. Lo","doi":"10.1109/EPTC.2013.6745802","DOIUrl":"https://doi.org/10.1109/EPTC.2013.6745802","url":null,"abstract":"The cost is always an important parameter for the new technical application. Through Si Via (TSV) technology becomes hot topic since image sensor application. We setup cost model according to our process flow and throughput for the cost study and reduction of 300mm TSI interposer. High cost area was calculated through the cost model. Full TSI process flow was separated as TSV, BEOL, Top UBM, TDDB, BSR, BS RDL& Bump sub-process flow. Top three high cost sub-process flow for 2.5D TSI with BEOL interconnect were identified from TSI process flow. Top three processes modules were isolated for each high cost subprocess flow. The high cost process modules were analyzed and explained in the paper. Two approaches were proposed for the cost reduction base on cost model analysis.","PeriodicalId":210691,"journal":{"name":"2013 IEEE 15th Electronics Packaging Technology Conference (EPTC 2013)","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116286525","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"The role of Cu-Al IMC coverage and aluminum splash in Pd-copper wire HAST performance","authors":"Ming-chuan Han, Jun Li, B. Yan, J. Yao, M. Song","doi":"10.1109/EPTC.2013.6745748","DOIUrl":"https://doi.org/10.1109/EPTC.2013.6745748","url":null,"abstract":"Copper wire bonding process has become popular interconnection process over gold because of its obvious cost advantages as well as lower electrical resistivity and good thermal conductivity. Recently, Pd-coated Cu wire is emerging as an alternative to bonding with bare Cu wire to prevent copper oxidation during the bonding and improve manufacturability [1]. Compared to bare copper, Pd copper wire shows robust bonding process, especially offers better 2nd bond performance and better reliability. Although copper wire bonding technology has been already at the phase of mass production, the discussion about reliability failures is still ongoing. The occurrence of the related open circuit failures are often reported as a consequence of humidity related stress test, Biased-HAST and PCT[2]. It is a specially challenge for the device with thicker bond pad metal. Most of open failure is caused by galvanic corrosion of one or more of intermetallic layers formed at the Cu-Al interface post HAST or Auto clave test. In this paper, a CMOS65 nm low k device with 47um fine pitch and 2.8um bond pad metal thickness was selected to establish indicator to pass HAST for the device with thicker bond pad metal. First, the distribution of the Pd on the surface was investigated under EFO parameter combination by HPM, SEM and EDX. Next, Capillary feature design was studied to shrink aluminum splash. Capillary with different MTA and chamfer angle were screened to know how these factors affect aluminum splash. Pro-stitch function of K&S ICONN also was studied to improve 2nd bond performance, bare copper as control. Third, the 1st bond parameters were optimized using selected capillary aimed to improve aluminum splash. Critical responses such as Ball size, Ball height, wire pull strength, ball shear strength, and stitch pull strength, cratering, IMC coverage and aluminum splash and remnant were studied to understand effect of Pd copper. DOE (Design of Experiment) and RSM (response surface methodology) was used to optimize the wire bond process. Thermal aging test coupled with wire pull and ball shear test with recording failure mode were studied. Last, four cells were built to be subject to HAST. The four cells were determined based on previous pass and failure, it covers different bonder platform, difference 1st bonding concept and different IMC coverage and aluminum splash. HAST& UHST pass rate, Ball shear, IMC coverage and aluminum as key wire bond response were studied. Studied shows Ball shear and IMC coverage are effective indicator to pass HAST and UHAST stress test. IMC coverage play main role in addressing moisture induced corrosion issue. Regarding IMC coverage, big void in ball center is not preferred and should be avoided. The gap between ball periphery and pad should be considered seriously.","PeriodicalId":210691,"journal":{"name":"2013 IEEE 15th Electronics Packaging Technology Conference (EPTC 2013)","volume":"193 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124302692","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Cu-Cu wire bonding challenges on MOSFET wafer technology","authors":"Tai Keen Chee, Kee Siew Theen, Tham Moong Sin","doi":"10.1109/EPTC.2013.6745728","DOIUrl":"https://doi.org/10.1109/EPTC.2013.6745728","url":null,"abstract":"Essentially, this paper presents the key challenges of monometallic Cu-Cu wire bonding process characterization for MOSFET thin wafer technology with bare Cu plated bond pad, on a leadframe package. And solutions to these challenges are presented and discussed. Generally, the technical challenges of bonding a 30um bare Cu wire on a bare Cu bond pad are lifted ball, NSOP and reliability failure related Cu bond pad oxidation. Inert atmosphere poses to be an important factor as Cu oxidizes readily. In this study, the wire bonder indexing and bonding stage configuration such Nitrogen (N2) gas input control, Cu kit, window clamp and top plate were examined for an optimum inert atmosphere control condition to prevent bare Cu free air ball (FAB) and Cu bond pad oxidation before wire interconnection is formed. The optimum N2 setting, 10 L/min in the N2 was obtained in this study for providing the protection to the Cu bond pad. A thin layer of 3.8nm for Cu2O was obtained from XPS depth measurement that caused NSOP and lifted ball. The finding implied that the differences of wire bond mechanism and process parameter characteristic from conventional wire bond system. Besides that, the hardness of both Cu FAB and Cu bond pad are also critical to form reliable bonding. The different material hardness of Cu FAB formation, bonded ball deformation and Cu bond pad were examined as a reference for process characterization. The reliability performance results of the Cu-Cu wire bonded specimens will be presented and discussed. In summary the study has demonstrated that Cu-Cu wire bonding is achievable but more work has to be done to improve the package reliability performance before large scale production, and potential cost saving.","PeriodicalId":210691,"journal":{"name":"2013 IEEE 15th Electronics Packaging Technology Conference (EPTC 2013)","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126337863","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Control of corrosion on aluminum MEMS structures after post etch clean","authors":"Lee Hou Jang Steven, Andrew Tan, D. Wei, V. Bliznetsov, Tham Dexian, Navab Singh, R. Murthy, E. Tan","doi":"10.1109/EPTC.2013.6745818","DOIUrl":"https://doi.org/10.1109/EPTC.2013.6745818","url":null,"abstract":"During the fabrication of aluminum MEMS (Microelectromechanical Systems) structures for display applications, surface corrosion or pitting appeared intermittently on the aluminum structures after aluminum (Al) plasma etch and post etch cleaning. Such surface corrosion severely limited the light reflecting capabilities of the planar aluminum micromirrors. The formulated organic solvent cleaners or post etch residue removers used after aluminum plasma etch such as NE14 from Air Products (AP) and ST250 from Advanced Technologies and Materials Incorporated (ATMI) were suspected to be the main culprits of the Al corrosion but without conclusive evidences. In order to better understand the causes of the post etch aluminum corrosion, extensive work has been carried out to look at the factors that may lead to Al corrosion after plasma etch and post etch clean. In particular, we have evaluated the surfaces of Al structures after NE14 and ST250 post etch cleaning using tools such as SEM and AFM. We focused on the three main aspects that may affect the Al corrosion: The Al plasma etch process, the extended cleaning in the organic solvent chemistries, and the Al corrosion as a result of water dilution in the organic solvent cleaners.","PeriodicalId":210691,"journal":{"name":"2013 IEEE 15th Electronics Packaging Technology Conference (EPTC 2013)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126392789","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Process development of 10μm pitch Cu-Cu low temperature bonding for 3D IC stacking","authors":"Ling Xie, S. Wickramanayaka, Hongyu Li, B. Jung, J. Aw, S. Chong","doi":"10.1109/EPTC.2013.6745769","DOIUrl":"https://doi.org/10.1109/EPTC.2013.6745769","url":null,"abstract":"A low temperature <;200°C Cu-Cu bonding process is developed for 3D IC stacking application. To prepare and activate good copper surface, three planarization processes and two surface treatment methods are studied in details and compared. Best surface treatment method is identified. It is found that good Cu-Cu direct bonding with high shear strength is achieved by the developed process and verified by the cross sectional structure. Low temperature Cu-Cu bonding for 3D IC applications is demonstrated by a high density Cu bump array structure with 10 μm pitch and 5 μm diameter. Chip-to-chip bonding approach is used for 3D IC stack bonding. Final cross sectional and daisy chain electrical measurement showed good connectivity of micro bump joints.","PeriodicalId":210691,"journal":{"name":"2013 IEEE 15th Electronics Packaging Technology Conference (EPTC 2013)","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126410233","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Double-sided Si-interposer with embedded thin film devices","authors":"J. Yook, Dongsu Kim, Jun-Chul Kim","doi":"10.1109/EPTC.2013.6745821","DOIUrl":"https://doi.org/10.1109/EPTC.2013.6745821","url":null,"abstract":"In this paper, a low-cost interposer technology is introduced which is a combination of PCB laminations and semiconductor thin-film processes. In advance, thin-film MIM capacitors are realized on the silicon surface by using standard thin-film process. After then, organic lamination and laser via drilling processes are used to make multi-layer signal and interconnections. Due to dual-side lamination process, the interposer has a symmetric structure and there are no warpages as increment of the number of signal layers. The fabricated interposer has an only 240 μm thickness and it has more than 8 metal layers. To demonstrate the interposer technology, a RF FEM is designed and realized by using the technology. In this module, thin film IPDs (Integrated Passive Devices) such as 2.45 GHz BPF and Balun are integrated in the front-side of the interposer, and a SPDT switch and 0603 chip capacitors are mounted on the back-side of the interposer.","PeriodicalId":210691,"journal":{"name":"2013 IEEE 15th Electronics Packaging Technology Conference (EPTC 2013)","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134115912","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Non-wetting of electroless nickel plating layer after reflow soldering process","authors":"L. E. Khoong, T. K. Gan","doi":"10.1109/EPTC.2013.6745808","DOIUrl":"https://doi.org/10.1109/EPTC.2013.6745808","url":null,"abstract":"Non-wetting of component with electroless nickel plating layer after reflow soldering process was analyzed. Components were observed to be skewed or dropped off from the solder pad of a board after soldering process. Failure mode was observed to be poor wetting and reaction between electroless nickel plating layer and solder pad. EDX and XPS analyses indicates that non-wetting of the components could be due to oxidation of the electroless nickel plating layer. Experiments carried shows that aging or oxidation of electroless plating layer play more significant role as compared to the thickness of electroless plating layer.","PeriodicalId":210691,"journal":{"name":"2013 IEEE 15th Electronics Packaging Technology Conference (EPTC 2013)","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133889303","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Signal integrity study of high density through silicon via (TSV) technology","authors":"B. E. Cheah, J. Kong, Chee Kit Chew, K. C. Ooi, S. Periaman","doi":"10.1109/EPTC.2013.6745684","DOIUrl":"https://doi.org/10.1109/EPTC.2013.6745684","url":null,"abstract":"This paper explores the electrical performance of several multi-channel TSV designs i.e. cross-etched full-plated TSV and cross-etched partial-plated TSV to further improve data transmission bandwidth among the vertically stacked silicon devices. The electrical characteristics of the multi-channel TSV designs were investigated and compared against the conventional TSV design in terms of return loss, insertion loss, near-end (NEXT) and far-end (FEXT) crosstalk. Fullwave electromagnetic simulation data showed the insertion loss performance of the multi-channel TSV designs are at par with the conventional TSV design up-to 50GHz. Meanwhile, the multi-channel TSV designs were found yielding improved NEXT and FEXT crosstalk performance. Transient analyses of respective TSV designs are also included in this paper for more conclusive discussions.","PeriodicalId":210691,"journal":{"name":"2013 IEEE 15th Electronics Packaging Technology Conference (EPTC 2013)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134045331","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Patterning of electroless copper deposition on low temperature co-fired ceramic","authors":"Dilshani Rathnayake-Arachchige, D. Hutt, P. Conway, M. D’Auria, S. Lucyszyn, R. Lee, I. Robertson","doi":"10.1109/EPTC.2013.6745796","DOIUrl":"https://doi.org/10.1109/EPTC.2013.6745796","url":null,"abstract":"The metallization of low temperature co-fired ceramic (LTCC) is typically done with commercially available silver or gold pastes using conventional screen printing processes. However, for some applications such as substrate integrated waveguides and high performance planar components where the metallization of vertical side walls is required, screen printing is difficult to apply. In such cases, electroless plating of copper can be employed to metallize the fired LTCC, which would also be a promising alternative to the high cost metals such as Ag and Au. In this study, electroless copper plating was combined with KrF excimer laser machining to deposit selective copper patterns on fired LTCC. Using this approach, a functional circuit was fabricated and electrically tested. The mask projection technique of the excimer laser can be used to create complex patterns on LTCC and initial work has been carried out to realize planar passive component layouts, including a capacitor and an inductor. The minimum feature size of the deposited copper that could be achieved in these designs was below 50 μm.","PeriodicalId":210691,"journal":{"name":"2013 IEEE 15th Electronics Packaging Technology Conference (EPTC 2013)","volume":"64 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131776634","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}