Fault isolation with backside polish for trench Schottky diode

Abstract

Photon Emission Microscopy (PEM) is one of the well-known fault isolation tool used in most failure analysis lab. The tool works on a principle whereby light will be emitted from the electron-hole pair recombination and carrier excitation when there is junction breakdown. However, this light emission is very weak causing fault isolation impossible to be detected on front side of Schottky diode wafer which is covered with thick Aluminium metallization. Therefore, a backside polishing method is required to thin the bulk Silicon to allow optimum transmission and thus failure site localization. In this study, Schottky diode wafer which has failed low (early) junction breakdown was thin down from total thickness of 640um. Final thickness of 40um does reveal an emission but do not able to show the die pattern. Emission was detected using InGaAs camera (λ=900nm to 1600nm). Die pattern is needed to be seen from the backside to be able to locate the exact fault localization spot on the front side. Die were further thin down to final thickness of 30um of total thickness including metallization. This paper will reveal the steps taken to polish die backside which is done by using ASAP-1 Ultratec sample preparation tool. Results showed that after thinning bulk Silicon to 30um with mirror finishing, die pattern was clearly visible. Fault localization done using PHEMOS 1000 where emission spot observed and samples were continued with cross-sectioning analysis. Cross-sectional analysis using Dual Beam system showed that there is Aluminium metallization diffused into mesa and trench region. Aluminium migration into these regions will cause high leakage and lowe (early) junction breakdown failure on the trench Schottky diode.