2013 IEEE 15th Electronics Packaging Technology Conference (EPTC 2013)最新文献

{"title":"The effect of Cu and Ag on the yielding behaviour of lead-free solders at high strain rates","authors":"K. Meier, M. Roellig, K. Wolter","doi":"10.1109/EPTC.2013.6745731","DOIUrl":"https://doi.org/10.1109/EPTC.2013.6745731","url":null,"abstract":"Electronics for automotive or mobile applications are exposed to vibration and shock loads causing PCB and interposer vibration. This leads to high strain rates within the component solder joints. It is known that solder joints show strain rate dependent yield behaviour [1-4] as well as that the strain rate dependency is dependent on the solder alloy composition. The solder joint alloy composition is determined by the solder paste and/or ball composition and the metallisation of the component and the substrate. There have been numerous publications on the strain rate depending yield behaviour of several alloy compositions used in industry. It has been shown that solder alloys behave more stiff and brittle if there is a higher silver content. Still, the direct dependency of yield behaviour and strain rate sensitivity on the silver and copper content has not been investigated and published yet. In this work the base material Sn99.9 and six lead-free solder alloys namely SnAg1.3 (wt.%), SnAg3.5, SnCu0.5, SnCu0.7, SnCu0.9 and SnAg1.3Cu0.5 have been studied for their yielding behaviour, strain rate sensitivity, deformation and fracture behaviour. Selected alloys have been tested in the as cast and isothermally aged state. The ageing was done at 150°C for 1000 h. Specimens were manufactured by casting applying fast cooling with 50 K/min. The specimen geometry as shown in figure 1 is a miniature dogbone shape to achieve a specimen micro- and grain structure comparable to solder joints. A high deformation speed tester introduced in earlier work [5] was utilised to conduct high strain rate experiments at rates from 20 to 800 s-1. High resolution online stress measurement revealed the strain rate dependent yielding behaviour. Fracture site inspection giving information on the damage behaviour was done by electron microscopy. The EBSD (electron backscatter diffraction) option was used to analyse the deformation behaviour at the grain structure level. Local fracture strain measurement revealed a very ductile behaviour of all specimens.","PeriodicalId":210691,"journal":{"name":"2013 IEEE 15th Electronics Packaging Technology Conference (EPTC 2013)","volume":"364 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131837805","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Test-time reduction methodology: Innovative ways to reduce test time for server products","authors":"Eric Dimaandal, Marco Padilla","doi":"10.1109/EPTC.2013.6745814","DOIUrl":"https://doi.org/10.1109/EPTC.2013.6745814","url":null,"abstract":"This paper deals with the challenges of implementing an innovative test-time reduction technique for the testing of server microprocessor products. In the testing of microprocessors, operating frequency and power calculations are done primarily during automated test equipment (ATE) insertion. This presents a significant opportunity to reduce test time because there is no generic or universal method to execute such flows, which are dependent on the ATE platform used. This paper provides an approach of smart/hybrid search and binning methodology used for both power-binning and speed-binning that reduced test time, and overall test cost, significantly. This has proved effective for the Sapphire test platform used by AMD in testing server-based microprocessor devices.","PeriodicalId":210691,"journal":{"name":"2013 IEEE 15th Electronics Packaging Technology Conference (EPTC 2013)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130946548","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Comparative study on delineation of Cu-Al intermetallic using chemical treatment and ion milling","authors":"L. Yeoh, Kok-Cheng Chong, Susan X. Li","doi":"10.1109/EPTC.2013.6745701","DOIUrl":"https://doi.org/10.1109/EPTC.2013.6745701","url":null,"abstract":"Intermetallic (IMC) is an alloy formed between two or more metals. Understanding IMC growth and formation is important in determining the bond integrity and the conductivity between metals. While Au-Al IMC is easily detected, Cu-Al IMC is hardly seen due to a slower interdiffusion rate between Cu and Al. This Cu-Al IMC can create a big challenge in analyzing suspected wire bond to bond pad interface failures, since defects may be difficult to find, and it makes delineating the different phases of IMC layers difficult. These limitations may lead to inaccurate findings and may result in invalid analysis conclusions. Chemical treatment has been proposed to be a good approach for IMC delineation. We evaluated the solution of hydrochloric acid (HCI) and isopropyl alcohol (IPA) with five different mixing ratios (4:1, 3:1, 2:1, 1:1, and 0:1 by volume) to delineate the Cu-Al IMC. Another methodology, focused ion beam (FIB) ion milling, is a surface preparation technique which uses an ion beam to strip away an extensive two-dimensional surface area for microscopic analysis. A comparative study was performed between chemical treatment and ion milling on the success of delineation of the Cu-Al IMC. Chemical treatment is a lower cost method which provides IMC delineation at a wider area (entire bonding interface), while ion milling is a higher cost method which does at a smaller area (selected bonding region). Both techniques are found to be very useful in IMC analysis for failure mechanism identification and root cause determination.","PeriodicalId":210691,"journal":{"name":"2013 IEEE 15th Electronics Packaging Technology Conference (EPTC 2013)","volume":"99 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132446175","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"AFM based methods for mechanical characterization of Nanothin films in electronics","authors":"Malgorzata Kopycinska-Muller, A. Striegler, N. Kuzeyeva, B. Kohler, K. Wolter","doi":"10.1109/EPTC.2013.6745749","DOIUrl":"https://doi.org/10.1109/EPTC.2013.6745749","url":null,"abstract":"We have developed a methodology to determine local indentation modulus M for films with thickness ranging from several nanometers to several hundreds of nanometers with nano-scale lateral resolution. Our results obtained for silicon oxide as well as porous organosilicate glasses were in a very good agreement with those provided by nanoindentation methods. The method used is the so-called atomic force acoustic microscopy (AFAM).","PeriodicalId":210691,"journal":{"name":"2013 IEEE 15th Electronics Packaging Technology Conference (EPTC 2013)","volume":"74 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127241449","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Challenges and optimization of 2nd bond process for reliable QFN packages","authors":"Norhanani Binte Jaafar, Eva Wai Leong Ching, Michelle Chew Bi-Rong, V. S. Rao, Daniel Rhee Minwoo","doi":"10.1109/EPTC.2013.6745800","DOIUrl":"https://doi.org/10.1109/EPTC.2013.6745800","url":null,"abstract":"As device technology is moving towards nano-IC technologies and consumer market are aggressively demands for the miniaturization of electronic products with more functionality [1], the requirement for small IC components has significantly increased, particularly on QFN (Quad Flat Non-leaded) packaging. Two major advantages of QFN over other leaded packages are (1) cost to manufacturer. Smaller, thinner and lighter package size is required to achieve more units per lead frame and (2) improved performance ICs since smaller packages will have smaller routing area, hence better thermal performance [2]. Other benefits of the QFN packages are low inductance and capacitor, smaller package volume and no external leads compare to the conventional leaded packages. QFN wirebonding has its own special characteristic as compare to other leaded packages. QFN wire bond process set-up is much more complicated than other packages and highly influence by three factors. They are clamping, lead bouncing and lead design. The challenge of QFN package is obtaining its process window without compromising on the 2nd bond quality. This paper specifically discusses the critical wirebonding parameters and capillary selection for QFN package using FA gold wire diameter of 1.0mils, breaking load range of 6.5 ~ 10.5g and elongation range of 2 ~6%. The main critical parameters discussed in this work are base ultrasonic power, base time and base force. Wire bonding process parameters are optimized to achieve wedge pull of > 4.0gf, no Non-Stick on Lead (NSOL), no heel crack and heel break observed. Destructive test such as wedge pull test is used to check the bonding quality. Failure modes are analyzed using high power optical scope microscope and Scanning Electronic Microscope (SEM).","PeriodicalId":210691,"journal":{"name":"2013 IEEE 15th Electronics Packaging Technology Conference (EPTC 2013)","volume":"14 6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115718000","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"An implementation of domain specific languages to microprocessor's Memory Built in Self Repair testing","authors":"Taufan Harist Dwijatmiko, Radford Nguyen","doi":"10.1109/EPTC.2013.6745750","DOIUrl":"https://doi.org/10.1109/EPTC.2013.6745750","url":null,"abstract":"Memory Built in Self Repair (MBISR) test in microprocessor testing has always been a very challenging. The main challenges are the complexity of the memory structure and the device to device design variations. Because of this complexity, separate groups with different focus are needed to address the challenge. The test engineers are the experts on Automated Test Equipment (ATE) platforms, while the IP owners are the experts on particular microprocessor's IP. To minimize the test program development and maintenance costs, the test engineers aim to provide a generic solution for all devices. Therefore, to cater for the variations, XML (Extensible Markup Language) has been used to represent the product specific definitions and configurations which will be maintained by the IP owners. However, the surge of new microprocessor designs and more advance innovation to the memory IPs lead to device to device variations increase. In the other hand XML is too static to handle these variations increase and has limited capability to express higher-order structures like conditionals. Therefore a domain specific language (DSL) is adapted to effectively deal with this issue. DSL as opposed to XML is a programming language which provides flexibility as offered by the general purpose languages, such as Java and C++. Yet, it is targeted to a particular kind of problem with its purpose of having separation of business and technical aspect, making it concise and easy to understand by the domain specialists. Therefore DSL fits perfectly as an easy to use language for the IP owners to express freely the product specifications. This paper showcases an example of DSL based solution to MBISR testing in microprocessor.","PeriodicalId":210691,"journal":{"name":"2013 IEEE 15th Electronics Packaging Technology Conference (EPTC 2013)","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115834587","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Intuitive and inexpensive method to evaluate flip chip bonding parameters of micro bump with wafer-level underfill material using glass substrate","authors":"J. Aw, S. Chong, Daniel Ismael Cereno, K. Teo, V. S. Rao","doi":"10.1109/EPTC.2013.6745716","DOIUrl":"https://doi.org/10.1109/EPTC.2013.6745716","url":null,"abstract":"Flip chip bonding of chips coated with wafer-level underfill over optically transparent glass substrate allows ease of inspection of flip chip bonding quality immediately, without the use of equipment such as SEM, CSAM or the need for highly-trained staff to interpret results. This method is inexpensive to implement, while intuitive to the engineer identifying responses to parametric changes in the flip chip bonding process. Our work complements the existing tomography techniques used to evaluate flip chip quality and reduces the amount of laborious cross-sectioning needed, adding new perspectives to evaluating flip chip bonding quality. We identified indicators of good bonding responses to our process parameters in bonding wafer-level underfill chips over glass substrate. This allows relationships to be quickly established and phenomena to be assigned. This evaluative method was inexpensive to implement, and with results that are intuitive to interpret.","PeriodicalId":210691,"journal":{"name":"2013 IEEE 15th Electronics Packaging Technology Conference (EPTC 2013)","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117094910","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Power distribution network modeling using block-based approach","authors":"Li Wern Chew","doi":"10.6117/KMEPS.2013.20.4.075","DOIUrl":"https://doi.org/10.6117/KMEPS.2013.20.4.075","url":null,"abstract":"A power distribution network (PDN) is a network that provides connection between the voltage source supply and the power/ground terminals of a microprocessor chip. It consists of a voltage regulator module, a printed circuit board, a package substrate, a microprocessor chip as well as decoupling capacitors. For power integrity analysis, the board and package layouts have to be transformed into an electrical network of resistor, inductor and capacitor components which may be expressed using the S-parameters models. This modeling process generally takes from several hours up to a few days for a complete board or package layout. When the board and package layouts change, they need to be re-extracted and the S-parameters models also need to be regenerated for power integrity assessment. This not only consumes a lot of resources such as time and manpower, the task of PDN modeling is also tedious and mundane. In this paper, a block-based PDN modeling is proposed. Here, the board or package layout is partitioned into sub-blocks and each of them is modeled independently. In the event of a change in power rails routing, only the affected sub-blocks will be re-extracted and re-modeled. Simulation results show that the proposed block-based PDN modeling not only can save at least 75% of processing time but it can, at the same time, keep the modeling accuracy on par with the traditional PDN modeling methodology.","PeriodicalId":210691,"journal":{"name":"2013 IEEE 15th Electronics Packaging Technology Conference (EPTC 2013)","volume":"58 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124666618","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Preparation of wafer-level LED packaging used uniform micro glass cavities by an improved Chemical Foaming Process (CFP)","authors":"Yu Zou, J. Shang, Yu Ji, Li Zhang, Chiming Lai, Dong Chen, Kim-Hui Chen","doi":"10.1109/EPTC.2013.6745850","DOIUrl":"https://doi.org/10.1109/EPTC.2013.6745850","url":null,"abstract":"Micro glass cavity has very important research values in many fields including Lighting Emitting Diode (LED) packaging, atomic devices, MEMS packaging and so on. In this study, an improved Chemical Foaming Process (CFP) have been investigated and uniform wafer-level micro glass cavities, which could be used in wafer-level LED packaging, have been prepared successfully by the proposed process. First of all, the fabrication process is introduced. Then the prepared uniform wafer-level semispherical glass cavity has been characterized by Atomic Force Microscopy (AFM) and mechanical shock test. And the result shows that the surface roughness of glass cavity is quite smooth which suits for optical applications as well as many other applications. At last, LED chip packaged with semispherical micro glass cavity on silicon substrate is presented.","PeriodicalId":210691,"journal":{"name":"2013 IEEE 15th Electronics Packaging Technology Conference (EPTC 2013)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124676563","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Investigation of interfacial phenomena of alloyed Au wire bonding","authors":"H. Kim, Minseok Song, K. Paik, J. Moon, J. Song","doi":"10.1109/EPTC.2013.6745766","DOIUrl":"https://doi.org/10.1109/EPTC.2013.6745766","url":null,"abstract":"Solid solution-type alloying in Au wire matrix is one of the well-known methods for improving the mechanical properties of Au wire as well as the reliability of bonding interface. Palladium (Pd) uses as a typical alloying element of Au bonding wire manufacturing which makes solid solution hardening effect in Au matrix. The behavior of Pd at the Au wire-Al pad bonding interface during the thermal aging, and the effect of Pd on Au/Al interfacial reactions were investigated. Two types of Au wires, Au-0.25wt%Pd (Low Pd content) and Au-0.95wt%Pd (High Pd content), were used for the fabrication of wire-bonded test vehicles (TVs). The wirebonded TVs were thermally aged at 175°C up to 1200hours, and the formation of a Pd-accumulation layer was investigated at Au-Al bonding interface by using a cross-sectional scanning electron microscope (SEM) and an electron probe microanalysis (EPMA). The accumulation of Pd atoms was confirmed at the TVs fabricated with the Au wire with high Pd content. According the results of a transmission electron microscope (TEM), the thickness of Pd accumulation layer was about 500nm and it located between Au wire (Au-0.95wt%Pd) and Au8Al3 intermetallic compound (IMC) layer. Au4Al IMC did not detected in Au-0.95wt%Pd wire TVs. In TV with Au-0.25wt%Pd wire, the phenomenon of Pd accumulation was not observed at bonding interface after thermal aging but Au4Al formed at the interface between Au-0.25wt%Pd wire and Au8Al3 IMC. After long-term thermal aging, the bonding interface was degraded by the oxidation phenomena. According to the cross-section analysis, it was mainly due to the oxidation of Au4Al IMC and, therefore, the Au-Al bonding interface becomes vulnerable to this kind oxidation.","PeriodicalId":210691,"journal":{"name":"2013 IEEE 15th Electronics Packaging Technology Conference (EPTC 2013)","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124880986","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}