Test-time reduction methodology: Innovative ways to reduce test time for server products

Abstract

This paper deals with the challenges of implementing an innovative test-time reduction technique for the testing of server microprocessor products. In the testing of microprocessors, operating frequency and power calculations are done primarily during automated test equipment (ATE) insertion. This presents a significant opportunity to reduce test time because there is no generic or universal method to execute such flows, which are dependent on the ATE platform used. This paper provides an approach of smart/hybrid search and binning methodology used for both power-binning and speed-binning that reduced test time, and overall test cost, significantly. This has proved effective for the Sapphire test platform used by AMD in testing server-based microprocessor devices.