2013 IEEE 15th Electronics Packaging Technology Conference (EPTC 2013)最新文献

{"title":"Optimization of etch-hole design for the thin film packaging","authors":"Jaewung Lee, J. Sharma, Wang Jian, Lim Leng Khoon, Navab Singh","doi":"10.1109/EPTC.2013.6745698","DOIUrl":"https://doi.org/10.1109/EPTC.2013.6745698","url":null,"abstract":"This paper reports the effect of the etch hole size, their distribution on cap layer and their quantity on the release time, down deformation of encapsulation after sealing. Uniform distribution of the etch hole in the centre of cap layer helps in reducing the release time. However, it results in a mass loading. Etch holes distributed at the edge of the Thin Film Encapsulation (TFE) help in protecting of the mass loading. However, it increases the release time of the TFE. So it is required to carefully arrange the etch holes on the cap layer in such way that mass loading on the MEMS device can be avoided and release time can also be minimized. The other aspect of this study is to check the downward deformation after sealing with a function of number of etch holes and their distribution of the cap layer. It is observed that a uniform distribution of etch hole in the cap layer helps in minimizing the stress and downward deformation of the encapsulation after the sealing process. For demonstrating the TFE, amorphous Si and SiO2 were used as a sacrificial layer and the cap layer, respectively. The etching of amorphous-Si (a-Si) sacrificial layer was performed with help of XeF2.","PeriodicalId":210691,"journal":{"name":"2013 IEEE 15th Electronics Packaging Technology Conference (EPTC 2013)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129789639","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Investigation of a microchannel-based cooling interposer for high-performance memory-on-logic 3DIC design","authors":"S. Melamed, Masaru Hashino, F. Kato, S. Nemoto, T. Bui, K. Kikuchi, H. Nakagawa, M. Aoyagi","doi":"10.1109/EPTC.2013.6745742","DOIUrl":"https://doi.org/10.1109/EPTC.2013.6745742","url":null,"abstract":"3D integrated circuits (3DICs) stack wafers vertically, allowing for heterogeneous integration with shortened wirelengths between multiple circuits. In memory-on-Iogic systems there is a significant concern that high-power sections of the processor will create large thermal gradients that cause logical failures in the stacked memory. In this paper we investigate the use of a microchannel-based interposer to cool the microprocessor while simultaneously decreasing the thermal gradient that the processor imposes on the memory. We have found that hotspots are relatively insensitive to design parameters when the processor die is 300 μm thick, however at a thickness of 10 μm the hotspot temperatures are highly dependent on the microchannel sizing and the thickness of the SiNR polymer layer that was used to seal the microchannels and bond the wafers.","PeriodicalId":210691,"journal":{"name":"2013 IEEE 15th Electronics Packaging Technology Conference (EPTC 2013)","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128326117","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Wire sweep characterization of multi-tier palladium-copper (Pd-Cu) wire bonding on LQFP package using low alpha green mold compound","authors":"S. S. S. Ali, S. Hian, B. C. Ang","doi":"10.1109/EPTC.2013.6745673","DOIUrl":"https://doi.org/10.1109/EPTC.2013.6745673","url":null,"abstract":"Controlling wire sweep is critical in transfer molding process as excessive results in shorting of wires, which in turn cause electrical failure. Therefore, understanding the effects of various factors on wire sweep is crucial to ensure processability and high yield for Pd-Cu wire production. In this study, wire sweep characterization carried out on Low Quad Flat Package (LQFP) package subject to various wire location, mold flow direction, wire length, wire pitch and wire angle. Fractional factorial design of experiment (DOE) is performed using 4 factors and 3 center points to identify key molding parameters which influence wire sweep. Wire sweep performance is also investigated under various mold cavity temperature, die thickness and wire loop height. Wire location is found to be the most significant factor that affects wire sweep percentage. A positive correlation is found for the wire length and wire sweep percentage. The prediction profiles show that longer transfer time improves wire sweep performance. Optimum mold parameters are identified using JMP statistical analysis software in order to improve the wire sweep performance. It is also noteworthy that a thicker 11 mils die gives better wire sweep performance compared to a 7 mils die. A mold cavity temperature of 175°C gives lower wire sweep percentage compared to 165 °C and 185°C. In conclusion, the wire located at segment F of corner 4 (mold gate at corner 1) experiences the worst wire sweep due to longer wire length and mold compound turning effect. Optimum compound fluidity, lower wire loop height and optimized molding parameters are determined to be the essential factors that improve wire sweep performance during mold encapsulation process.","PeriodicalId":210691,"journal":{"name":"2013 IEEE 15th Electronics Packaging Technology Conference (EPTC 2013)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129566107","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A shielding structure with conductive adhesive coated on molding compound in 3D package","authors":"Jun Li, Jie Pan, Liqiang Cao, Xueping Guo, Tianmin Du, Yuan Lu, L. Wan","doi":"10.1109/EPTC.2013.6745832","DOIUrl":"https://doi.org/10.1109/EPTC.2013.6745832","url":null,"abstract":"As electronic products tend to higher density, smaller area, lighter weight, and etc., three-dimensional (3D) packages are becoming effective chooses. Advanced 3D package technologies make the electronic products smaller with high density, but bring in more serious problems. The electromagnetic interference (EMI) is an important issue for more complex electromagnetic environment and smaller distance between noisy sources and sensitive circuits in the 3D package, especially in mixed signal system or RF/Microwave system. In this paper, a shielding structure with conductive adhesive covered on molding compound is researched. The shielding structure contains the molding compound, the conductive adhesive, and the ground plane and grounding vias. The conductive adhesive coated on the molding compound, and connects the ground plane or grounding vias on the top of substrate. To study the shielding performance, Device Under Tests (DUTs) are designed and fabricated in this paper. The test dies with Electro-Magnetic Coil are fabricated for DUTs to compare the isolation effect. The shielding performance of DUTs is measured by test system, which contains Vector Network Analyzer (VNA), coaxial cables and DUTs. The shielding efficiency (SE) of the novel structure is about 25dB below 8GHz, and the SE for high frequency is relative higher due to skin depth decreasing. The process of hybrid package with shielding structure is compatible with the normal package technology. The only additional step is the conductive adhesive coating. It is an effective method for suppressing near field noise in 3D mixed signal or RF/ Microwave package.","PeriodicalId":210691,"journal":{"name":"2013 IEEE 15th Electronics Packaging Technology Conference (EPTC 2013)","volume":"488-489 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127229210","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Development of package level hybrid silicon heat sink for hotspots cooling","authors":"B. L. Lau, Y. J. Lee, Yong Han, Y. Leong, K. F. Choo, Xiaowu Zhang, P. Chan","doi":"10.1109/EPTC.2013.6745819","DOIUrl":"https://doi.org/10.1109/EPTC.2013.6745819","url":null,"abstract":"In this paper, the fabrication of package level silicon microchannel heat sink for hotspot thermal management is presented. These include the design, micro fabrication process and chip level integration of a hybrid silicon heat sink, which integrates jet impingement, microchannel cooling technologies. The fabrication of hybrid heat sink is proposed by bonding two Si chips which patterned with nozzle and microchannel structures separately. The nozzle array is fabricated using though silicon vias (TSV) process. This nozzle plate is used to generate jet impingement effect into the microchannel heat sink. On the other hand, the microchannel heat sink consists of micro fins and channels which are fabricated using deep reactive ion etch (DRIE) process. The micro fins increase the area for convective heat transfer while the micro channels serve as the liquid conduit to carry the intense heat away from the heat source. Two silicon chips are bonded using thermal compression bonding (TCB) process. For the packaging, the integration of thermal chip and diamond heat spreader onto silicon heat sink is performed using gold-tin eutectic bonding through TCB process. In this paper, the major fabrication steps and critical process parameters will be discussed in details along with the hydraulic test and thermal analysis.","PeriodicalId":210691,"journal":{"name":"2013 IEEE 15th Electronics Packaging Technology Conference (EPTC 2013)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130980318","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"R1 — A reliability comparison study between 14 lead free alloys","authors":"H. Wohlrabe, G. Reichelt","doi":"10.1109/EPTC.2013.6745730","DOIUrl":"https://doi.org/10.1109/EPTC.2013.6745730","url":null,"abstract":"The reliability of solder joints is one important part of the quality of SMT-Boards. The paper presents a reliability study named R1. The base of the study is a reliability experiment with 14 different solder alloys (13 lead free solders and a Sn63 alloy as a reference), six different surfaces, six different SMD-chips combined with three different pad layouts. A high cycle reliability test was used. The times of failures were evaluated with the Weibull analysis followed by an analysis of variance.","PeriodicalId":210691,"journal":{"name":"2013 IEEE 15th Electronics Packaging Technology Conference (EPTC 2013)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128774229","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"The study of backside TSV reveal process by direct Si/Cu grinding and polishing","authors":"K. Xue, Daquan Yu, Yuesheng Li, Feng Jiang, Haiyan Liu, Qibing Wang, Fengwei Dai","doi":"10.1109/EPTC.2013.6745826","DOIUrl":"https://doi.org/10.1109/EPTC.2013.6745826","url":null,"abstract":"Despite the fact that manufacturing processes of through silicon via (TSV) have achieved great progresses, the backside via reveal process is still challenging and costly. The simplest TSV reveal method is using backside grinding (BG) and chemical mechanical polishing (CMP), by which the vias are revealed by CMP directly after wafer thinning with BG. However this method is not well accepted due to the Cu contamination concern. From the application point of view, if the Cu contamination is restrained in pretty low level with process optimization, it may be still possible to be applied to achieve the simple and economical process, especially for 2.5D interposer manufacturing which is more tolerant with Cu contamination. In this work, very low contamination level-copper atoms (lower than 0.000001%) were got in backside wafer surface after CMP of TSV vias, which is good enough for interposer or even 3DIC application.","PeriodicalId":210691,"journal":{"name":"2013 IEEE 15th Electronics Packaging Technology Conference (EPTC 2013)","volume":"468 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123281611","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"The characteristics and factors of a wafer dicing blade and its optimized interactions required for singulating high metal stack lowk wafers","authors":"K. Shi, K. Yow","doi":"10.1109/EPTC.2013.6745714","DOIUrl":"https://doi.org/10.1109/EPTC.2013.6745714","url":null,"abstract":"Dicing a thick, 6 metal layer low-k Cu metallization wafer (from 90nm node wafer technology) is very challenging compared to the 4 metal layer stacked wafer. Poor topside cutting responses with excessive saw chip-outs were observed with the 6 metal layer. To resolve the saw chipping quality issue, a series of dicing assessments were performed, which includes: (1) saw machine baseline calibration and verification, (2) analysis study on the blade's elements (diamond grit, diamond concentration, bond type) (3) new saw blade selection and evaluation, and (4) saw process parameter optimization and validation. This paper is focused on discussing the fundamentals of understanding each of the blade elements and its interaction on improving the topside chipping and peeling quality. Experimental studies were conducted by using various blade types and by varying the blade element composition. This includes variations in diamond grits sizes, diamond concentration (higher vs. lower diamond concentration), and bond type (softer vs. harder bond). A thorough process characterization was conducted to validate the cutting performance on the post-processed wafers. All results and data collected from the experimental studies were statistically analyzed and interpreted. In conclusion, a new saw blade with the appropriate selected blade attributes were introduced and qualified. With the optimized blade and saw parameters for the thick low-k Cu metallization wafers, topside chipping and peeling quality was significantly improved.","PeriodicalId":210691,"journal":{"name":"2013 IEEE 15th Electronics Packaging Technology Conference (EPTC 2013)","volume":"557 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123128455","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Electrochemical assembly and molecular dynamics simulation of SAM on copper for epoxy/copper adhesion improvement","authors":"Stephen C. T. Kwok, M. Yuen","doi":"10.1109/EPTC.2013.6745759","DOIUrl":"https://doi.org/10.1109/EPTC.2013.6745759","url":null,"abstract":"This work reports on adhesion enhancement effects of self-assembled organothiol treatment on copper (Cu)/epoxy interface, as well as a significant reduction in treatment time under the influence of electric potential. The interfacial adhesion has 20-fold enhancement through the treatment due to improved linkage between copper substrate and epoxy layer by chemisorbed organothiol molecules. The treatment time was greatly reduced by a factor 32 from 16 hours to 30 minutes thanks to the electrical field assisted method without compromising the maximum adhesion strength, which was shown to be in order of 97.2Jm-2. Molecular Dynamics (MD) simulations were also carried out for studying the surface coverage effect of Self-assembly Monolayer (SAM) on Cu surface towards adhesion strength between Cuiepoxy interface. Simulation results together with experimental data were then used for explaining the adhesion promotion mechanism between Cu/epoxy interface.","PeriodicalId":210691,"journal":{"name":"2013 IEEE 15th Electronics Packaging Technology Conference (EPTC 2013)","volume":"422 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122464354","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Study of die bond on roughened NiPdAu-Ag pre-plated frame with anti-EBO","authors":"Raymond Solis Cabral, Joseph Aaron Mesa Baquiran, Wu-Hu Li, Ariel Lizaba Miranda, M. Mercado","doi":"10.1109/EPTC.2013.6745739","DOIUrl":"https://doi.org/10.1109/EPTC.2013.6745739","url":null,"abstract":"This paper studies the challenges and behavior of epoxy material between the silicon (Si) material and roughened Ni/Pd/Au-Ag alloy-plated Copper (Cu) leadframe (known as μPPF) with anti-epoxy bleed-out (EBO) during die bond process. Die bond on die attach paddle (DAP) of roughened μPPF using Silver (Ag)-based epoxy has been a challenge for its manufacturability in terms of maintaining the target epoxy fillet height for a 300 μm Si chip thickness. The study on the roughened μPPF utilizing die bond parameters for Ag-based epoxy on standard Ag-plated DAP Cu leadframe yielded fillet height greater than the maximum target limit of 75% of die thickness and reaching as high as 100% fillet height. This occurrence leads to risks of epoxy component creeping onto the chip surface which is detrimental on reliability (delamination on die top) and can cause manufacturing yield loss due to die contamination and non-stick on pad (NSOP) during wire bonding. The processability of the epoxy on the surface of the roughened μPPF leadframe needs to be established due to this significant difference in fillet height result when compared to the Ag-plated Cu leadframe which has a major impact in the quality of the chip assembly. The development of the die bond process for the roughened μPPF is separated into two assessments, namely epoxy dispense scale assessment and die bond parameter design of experiment (DoE). The epoxy dispense scale assessment studies the optimum epoxy glue coverage with respect to chip area that will ensure a consistent epoxy volume underneath the Si chip (bond line thickness or BLT) and achieving a linear epoxy fillet height formation along the sidewall of the Si chip. Once the optimum dispense scale is established via DoE, the critical die bond parameters identify a parameter window where a controlled fillet height is observed without any impact on the functionality test response of the epoxy. The study shows that a high epoxy dispense scale and optimum die bond parameter, namely, component over travel distance and dispensing height are required to achieve an optimum epoxy fillet height control along the side wall of the Si chip.","PeriodicalId":210691,"journal":{"name":"2013 IEEE 15th Electronics Packaging Technology Conference (EPTC 2013)","volume":"84 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122940698","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}