Investigation of a microchannel-based cooling interposer for high-performance memory-on-logic 3DIC design

Abstract

3D integrated circuits (3DICs) stack wafers vertically, allowing for heterogeneous integration with shortened wirelengths between multiple circuits. In memory-on-Iogic systems there is a significant concern that high-power sections of the processor will create large thermal gradients that cause logical failures in the stacked memory. In this paper we investigate the use of a microchannel-based interposer to cool the microprocessor while simultaneously decreasing the thermal gradient that the processor imposes on the memory. We have found that hotspots are relatively insensitive to design parameters when the processor die is 300 μm thick, however at a thickness of 10 μm the hotspot temperatures are highly dependent on the microchannel sizing and the thickness of the SiNR polymer layer that was used to seal the microchannels and bond the wafers.