2013 IEEE 15th Electronics Packaging Technology Conference (EPTC 2013)最新文献

{"title":"Investigation on decap shift and incomplete fill issues in the wafer level compression molding process","authors":"L. Bu, S. Ho, Sorono Dexter Velez, Boyu Zheng, S. Chong, Booyang Jung, T. Chai, Xiaowu Zhang","doi":"10.1109/EPTC.2013.6745824","DOIUrl":"https://doi.org/10.1109/EPTC.2013.6745824","url":null,"abstract":"Decaps are the panacea to cure the noise related issues. Due to the short distance advantage, decaps were embedded in the package instead of PCB. These decaps, generally having higher thickness than chips, would play a vital role in the wafer level molding process. Improper population will cause decap shift and incomplete fill issues. In the present paper, proper arrangement of decaps were designed and optimized. The results show that decaps placed along two adjacent sides rather than two opposite sides of the chip would result in better filling. In order to further reduce the drag force on decaps, chip to decap distance should be as large as possible. This implies that narrow gaps would result in higher drag force. Therefore, narrow gaps should be avoided to ease the drag force in the package as well as the whole wafer.","PeriodicalId":210691,"journal":{"name":"2013 IEEE 15th Electronics Packaging Technology Conference (EPTC 2013)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127612484","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Single current source electromigration system and its application to copper pillars with tin based solder","authors":"A. Trigg, C. T. Chong, Hsiao Hsiang Yao, Yaw Jyh Tzong","doi":"10.1109/EPTC.2013.6745702","DOIUrl":"https://doi.org/10.1109/EPTC.2013.6745702","url":null,"abstract":"The trend towards finer pitch interconnections in current generation microelectronic packaging, coupled with the introduction of 3D chipstacks and high power ICs operating at low voltage have all contributed to increasing current density in conductors to the extent that electromigration is a threat to long term reliability. Traditional electromigration (EM) test systems were designed for back end of line (BEOL) IC interconnect with dimensions of micrometres or less and so typically were limited to a total current of 25 mA per device under test (DUT). However for packaging applications, higher currents, 100mA to 1A, are typically needed to provide sufficient current density to generate electromigration failures. Because the traditional EM test systems use dedicated source-measure units for each individual DUT, they are expensive and cannot easily be modified to provide higher currents or to support different package types. In this paper we describe an alternative approach to package EM testing in which a single current source supports many DUTs while the resistance measurements are obtained using a separate multimeter accessing the DUTs by means of a software controlled switch matrix. This provides a flexible, easily reconfigurable system at a cost of approximately 10% that of a traditional system. Since many reliability test labs already have many of the components needed the cost can be reduced still further.","PeriodicalId":210691,"journal":{"name":"2013 IEEE 15th Electronics Packaging Technology Conference (EPTC 2013)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133495585","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Investigation of dynamic and mechanical thermal behavior of isotropic conductive adhesives","authors":"R. Durairaj, Chew Chee Sean, Tan Chia Chiun, L. Ping","doi":"10.1109/EPTC.2013.6745763","DOIUrl":"https://doi.org/10.1109/EPTC.2013.6745763","url":null,"abstract":"Isotropic conductive adhesive (ICAs) are considered as the most promising replacement to lead or lead free solders due to relatively low melting point, simple processing, low processing temperature and fine pitch capability. The study aims to instigate the dynamic mechanical and thermal properties of diglycidylether of bisphenol-A (DGEBA) and polyurethane (PU) based ICAs. Dynamic mechanical thermal analysis (DMTA) is one of the ways to estimate changes, which occur for polymeric materials in the broad range of temperature and frequency of changes in load. In this study, the results showed that measurement of storage modulus, loss modulus and also damping factor of the samples formulated with DGEBA has better thermal mechanical properties than the samples formulated with PU. In addition, by changing the conventional silver flakes to silver nanoparticles; the results shows that nanoparticles make a little improvement in thermal mechanical properties for the temperature beyond Tg. For silver flake formulation with DGEBA, the result shown that the samples with higher volume fraction of silver flake shows a better thermal mechanical properties.","PeriodicalId":210691,"journal":{"name":"2013 IEEE 15th Electronics Packaging Technology Conference (EPTC 2013)","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133111746","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Effect of palladium on the mechanical properties of Cu and Cu-Al intermetallic compounds","authors":"A. B. Lim, Xin Long, Lu Shen, X. Chen, R. Ramanujan, C. Gan, Zhong Chen","doi":"10.1109/EPTC.2013.6745727","DOIUrl":"https://doi.org/10.1109/EPTC.2013.6745727","url":null,"abstract":"There is a growing interest in copper (Cu) wire bonding due to its significant cost savings over gold wire. However, concerns on package reliability and corrosion susceptibility have driven the industry to develop alternative materials. Recently, palladium coated copper wire (Pd-Cu) wire has seen rapid entry into the market as it is believed to improve reliability of copper wire bonds on aluminum (Al) pads. However, the effect of palladium on the mechanical properties and corrosion resistance of Cu and Cu-Al intermetallics has not been studied in detail. In this paper, bulk alloys of Cu and Cu-Al with different concentrations of Pd were prepared under controlled conditions to simulate the intermetallics (IMC) formed between the copper ball bond and aluminum pads during bonding. Material properties such as elemental composition and phase formation were analyzed. Hardness and Young's modulus of the alloys were characterized by nanoindentation. It was observed that CuAl intermetallic is the hardest and stiffest. Palladium was observed to slightly increase the modulus and hardness of the alloys.","PeriodicalId":210691,"journal":{"name":"2013 IEEE 15th Electronics Packaging Technology Conference (EPTC 2013)","volume":"202 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116170033","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Impact of Ag plated surface roughness towards die bond and wire bond","authors":"Goh Chen Liew, Khoo Ju Lee, Yeo Kian Hong, M. Aileen, L. Ming","doi":"10.1109/EPTC.2013.6745849","DOIUrl":"https://doi.org/10.1109/EPTC.2013.6745849","url":null,"abstract":"Lead delamination is one of the major challenges faced in semiconductor manufacturing. It happens when there is a separation between silver plated surface (Ag) and encapsulation molding compound (EMC) inside a package. One of the most common approach that were often used is through roughening of Ag surface to improve the mechanical interlocking between Ag surface and EMC [1]. However, the characteristic of Ag surface roughness towards die bond and wire bond performance is not studied in depth. In this paper, evaluation will be done to check the characteristic of Ag surface roughness towards die bond and wire bond process. Relative average roughness (Sa) of the Ag surface will be measured prior to the evaluation. Leadframes with different Sa will be used for each evaluation leg. During die bond process, the condition of surface prior bonding has significant implications towards the quality of the bonds formed. The peak to valley texture of Ag surface is able to affect the mechanical bonding between leadframe and adhesive epoxy. Therefore, die shear test will be done to check the bonding quality of the interface bond. In addition, correlation between Sa towards bond line thickness (BLT) and epoxy bleed out (EBO) will be assessed due to different surface roughness will influence the conformity of the epoxy to the surface. Xray will be done at 0hour and after Temperature Cycle (TC) to check for potential voids caused by different surface roughness. In wire bond, due to the characteristic of Ag, the bonding between Au wire and Ag plated surface is reliable and does not form intermetallic compounds (IMC) at high temperature. [2]. Despite the reliability of the bonding, the impact of surface roughness towards 2nd bond is not fully understood. The ultrasonic power applied on different Ag roughness during wire bond process will induce different friction power density at the bonding interface. It is believed that different friction power will initiate different mechanical interlocking between Au and Ag. Therefore, stitch pull test and Non stick on Lead's (NSOL) ppm will be collected during the study to check the correlation between 2nd bond quality and Ag roughness. The stitch integrity after stress was investigated through two temperature extreme of Temperature cycle (TC) test. Focused ion beam (FIB) analysis will be done to correlate the adhesion between Au and Ag for different surface roughness. Besides, it is predicted that 2nd bond cutting will be less consistent when the surface is rougher. This will lead to inconsistent Free Air Ball (FAB) size and thus impact 1st bond. Therefore, FAB size will be collected through scanning electron microscope (SEM). This paper will present as a fundamental guideline to control Ag surface roughness without compensating the quality at die bond and wire bond processes.","PeriodicalId":210691,"journal":{"name":"2013 IEEE 15th Electronics Packaging Technology Conference (EPTC 2013)","volume":"78 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115273532","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Effect of vacancy defects on thermal conductivity of single-walled carbon nanotubes","authors":"Kai Tang, F. Zhu, Youkai Chen, Ying Li, H. Liao, Xiahui Chen, Sheng Liu","doi":"10.1109/EPTC.2013.6745835","DOIUrl":"https://doi.org/10.1109/EPTC.2013.6745835","url":null,"abstract":"The existence of structure defects can be influence to properties of carbon nanotubes (CNTs). Effect of vacancy defects on heat conduction in CNTs is revealed by nonequilibrium molecular dynamics (NEMD) simulations. The thermal conductivity of (6,6) single-walled carbon nanotubes (SWCNTs) with various numbers of vacancy defects is investigated in this work. It is demonstrated that the thermal conductivity of SWCNTs with vacancies is lower than that of perfect SWCNTs. Thermal conductivity of SWCNTs deceases with increasing concentration of vacancy defects, it is noted that thermal conductivity of SWCNTs can be a 45% decreases with 0.16% vacancy defects at 300K. It is also illustrated that the thermal conductivity of SWCNTs decreases with the increasing temperature.","PeriodicalId":210691,"journal":{"name":"2013 IEEE 15th Electronics Packaging Technology Conference (EPTC 2013)","volume":"161 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115396259","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"CVQFN package development","authors":"J. Ho","doi":"10.1109/EPTC.2013.6745674","DOIUrl":"https://doi.org/10.1109/EPTC.2013.6745674","url":null,"abstract":"DR-QFN / MR-QFN, is a conventional leadframe based QFN package in Dual-row / Multi-Row design, which provides QFN package configuration with higher IO up to ~100 counts. At present, TI (Texas Instrument) has been providing polyimide tape type substrate with Ball Grid Array package named as MicroStar Junior BGA™(u*JrBGA™) for 100 more IO counts requisition. By applying the concept of Cu trace routing in polyimide tape substrate of u*JrBGA™™ instead of the ordinary QFN leadframe and then filling with solder resist (SR), an advanced multi-row QFN package is then reborn to support for more IO pin counts in QFN configuration. And package total thickness could be thinning down to 0.4mm. This advanced multi-row QFN package is named as Cu via QFN (CVQFN). Apart from the standard etching process for leadframe (Cu trace) routing, the leadframe (Copper Trace) for CVQFN adopts the plating process. Solder resist filling process is another employed process to sustain the 75 um thin leadframe (Cu trace) for the rest assembly process. Affirmatively, the goal is achieved to compete with current Dual-row / Multi-Row QFN (DRQFN/MRQFN) by offering the same thermal dissipation, package outline and foot print pattern. It also provides ultra thin package solution. Package reliability, Assembly manufacturability, and SMT BLR are discussed in this report. This report also describes this CVQFN can get rid of the mold flash issue existed in conventional MR-QFN/DR-QFN.","PeriodicalId":210691,"journal":{"name":"2013 IEEE 15th Electronics Packaging Technology Conference (EPTC 2013)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123881916","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Forming solder filet on leadframe edges of a QFN with immersion tin","authors":"M. Ozkok, H. Mertens, J. Bender, M. Bruder","doi":"10.1109/EPTC.2013.6745805","DOIUrl":"https://doi.org/10.1109/EPTC.2013.6745805","url":null,"abstract":"The QFN package is one of several package technologies that connect ICs to the surfaces of PCBs without through-holes. The standard QFN Package soldered on a PCB is shown on fig. 1 a). The side edges of th. QFN are not covered by solder, which results in the fact that the package is soldered only planar in: dimensions from the QFN bottom side onto the PCB as shown on fig. 1 b). The QFN were the side edge is covered by immersion tin will keep the side edged of a QFN solderable. This allows the package to be soldered in 3 dimensions onto the PCB providing a stronger solder joint and; better reliability. The suggested paper describes a new process to cover the side edges of the package with immersion tin after the QFN package singulation step. The exposed lead frame edges are covered by immersion tin. No exposed copper is visible and delivers a three dimensional solder joint with better reliability and protection for the soldered package.","PeriodicalId":210691,"journal":{"name":"2013 IEEE 15th Electronics Packaging Technology Conference (EPTC 2013)","volume":"61 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126174560","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Signaling scheme for high speed die-to-die interconnection in multi-chip package (MCP) technology","authors":"K. Yong, B. E. Cheah, W. Song, M. F. Ain","doi":"10.1109/EPTC.2013.6745707","DOIUrl":"https://doi.org/10.1109/EPTC.2013.6745707","url":null,"abstract":"Multi-chip package (MCP) technology has recently advanced as an alternative packaging solution to enable high performance and power-efficient mobile electronic devices. The wide adoptions of MCP technology are mainly driven by reduced circuit complexity, heterogeneous integration across different silicon process technology and shorter product cycle time. However, the high density on-package die-to-die (D2D) interconnects within package presents unique signaling challenges as the operating frequency continue to rise. This paper analyzes various low power passive signaling enhancement techniques e.g. equalization and termination to mitigate the signal integrity challenges of the high speed on-package D2D channels. The effectiveness of various signaling enhancement techniques and topologies were studied and compared in terms of eye opening and overshoot performances. The combination of series-source termination and parallel-load termination was found to be a feasible candidate in view of optimum trade-off between performance and silicon real-estate or costs. Simulation results show the recommended topology is able to achieve 300mV/40ps eye opening at 15Gbps.","PeriodicalId":210691,"journal":{"name":"2013 IEEE 15th Electronics Packaging Technology Conference (EPTC 2013)","volume":"347 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126031385","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Simultaneous molding and under-filling for void free process to encapsulate fine pitch micro bump interconnections of chip-to-wafer (C2W) bonding in wafer level packaging","authors":"Dexter Velez Sorono, S. Vempati, L. Bu, S. Chong, C.T.W. Liang, Seit Wen Wei","doi":"10.1109/EPTC.2013.6745686","DOIUrl":"https://doi.org/10.1109/EPTC.2013.6745686","url":null,"abstract":"The encapsulation of chips with fine pitch micro bump interconnections in chip-to-wafer (C2W) bonding has a known two steps process in wafer level packaging. First step is underfilling process that fills the gap between bumps underneath the chips. Under-filling process can either be using liquid dispensing which allow it to flow underneath the bumped chips by capillary force or using a non-flow under-fill material. The second step is molding process that encapsulates the entire C2W with a molding compound. Through simultaneous molding and under-filling process to encapsulate, the two steps will become a single step process. Although, this method has been widely used for flip-chip Ball Grid Array (BGA) packaging using Moldable Under-fill (MUF) material in transfer molding, it is not yet fully utilized for wafer level C2W packaging using MUF material in wafer level compression molding. One major challenge during under-filling is voids formation underneath the bumped chips as shown in Fig. 1. This study aims to implement simultaneous molding and under-filling to achieve a void free process in wafer level C2W packaging. Mold flow simulation using ANSYS FLUENT 14.5 commercial software is being used to predetermine the major factors affecting the voids formation. Based on the simulation result, we have identified several factors that can significantly affect the voids size. The identified factors are mold temperature, mold compound dispensing pattern and mold filling speed. The mold flow simulation results are being validated using test chips with 90um micro bump pitch in the actual molding experiment. We validated the actual void formation by comparing the result of low and high molding temperature, comparing round and straight line dispensing pattern and also validated the use of slower filling speed during molding process. The experimental result confirms the total elimination of voids formation during simultaneous molding and under-filling process. The experimental result indicates that the actual molding perfectly match with the mold flow simulation result.","PeriodicalId":210691,"journal":{"name":"2013 IEEE 15th Electronics Packaging Technology Conference (EPTC 2013)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129398379","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}