2013 IEEE 15th Electronics Packaging Technology Conference (EPTC 2013)最新文献

{"title":"Analysis of thermal evolution in power semiconductor modules as lifetime and reliability tool","authors":"M. Pieschel, Y. Gerstenmaier, G. Mitic, M. Neumeister, J. Seidel","doi":"10.1109/EPTC.2013.6745732","DOIUrl":"https://doi.org/10.1109/EPTC.2013.6745732","url":null,"abstract":"A method is presented for temperature calculations in systems with irregular rapidly varying chip-powers by solution of implicit integral equations, where the dissipated power may depend on chip-temperature itself. For discontinuous power evolution differential equation solvers pose problems in treating thermal equivalent circuits. When no thermal model exists, the method can start directly from measured cool down curves. For user specified mission profiles over long duration, semiconductor module lifetimes are estimated by thermal cycle counting and application of the Palmgren-Miner-rule. For simplified models of chip power dissipation thermal runaway can be observed in case of unfortunate system parameters. A general criterion is inferred for the thermal stability of the system with the help of a quasi steady-state model for the system's cooling power described by a single thermal resistor.","PeriodicalId":210691,"journal":{"name":"2013 IEEE 15th Electronics Packaging Technology Conference (EPTC 2013)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128521073","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Effect of die attach material on heavy Cu wire bonding with Au coated Pd bond pad in automotive applications","authors":"B. S. Kumar, A. Albert, L. H. Lim","doi":"10.1109/EPTC.2013.6745794","DOIUrl":"https://doi.org/10.1109/EPTC.2013.6745794","url":null,"abstract":"Copper (Cu) is rapidly gaining an increasing market share as an interconnect material in semiconductor packaging because of its major advantages over gold (Au). When replacing part of the bond pad with a noble metal, Cu bonding wire is of particular interest due to its superior electrical properties, lower cost and higher mechanical properties as compared with Au. Extensive work and analysis are needed at the onset of the packaging development phase to meet the right level of manufacturability and reliability requirement. Wire bond process optimization commonly focus around bond time, bond force and bond power. Other factors generally evaluated for copper wire bonding include incoming bond pad cleanliness, bonding pad surface oxidation, wire oxidation during electronic flame off and forming gas flow rate. A lesser known variable, die attach, is often overlooked in packaging with Cu wire. However, die attach (DA) materials that have comparatively low modulus and high elastic properties at elevated temperature (above Tg) can cause problems at wire bonding process temperatures. In this paper three DA material types were evaluated using 50 um Cu wire bonding and main focusing responses of non stick on pad (NSOP) and ball shear strength (BST) as well investigates various process factors in achieving a reliable Cu wire bonding on heavy Cu wire bonding with Au coated Pd bond pad in automotive applications. The results showed that a significant influences from the DA material properties which affecting the wire bonding performance. DA Soft solder are better due to solder has higher elastic modulus (MPa) in even remain at higher bonding temperature. However Polymeric DA1 has comparatively low modulus and high elastic properties in elevated temperature can cause NSOP and low ball shear in smaller chip sizes at higher bonding temperature.","PeriodicalId":210691,"journal":{"name":"2013 IEEE 15th Electronics Packaging Technology Conference (EPTC 2013)","volume":"70 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128639602","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A novel damage test evaluation of IC bond pad stack strength","authors":"A. Yeo, Eric Yong, Dan Swee Tong, G. M. Reuther","doi":"10.1109/EPTC.2013.6745680","DOIUrl":"https://doi.org/10.1109/EPTC.2013.6745680","url":null,"abstract":"A novel damage test method is presented, to examine the mechanical strength or behavior of an Integrated Circuit (IC) bond pad stack. A micro-mechanical tester is employed for an indentation test where quasi-static load is applied on the IC bond pad. Any damage or cracking can be detected by the acoustic emission (AE) sensor system placed underneath the IC chip. This methodology provides an in-depth understanding of the damage mechanics and emergence in a complex structure as in the IC chip bond pad stack. As a consequence, weak designs or mechanically inferior layouts can be identified and avoided.","PeriodicalId":210691,"journal":{"name":"2013 IEEE 15th Electronics Packaging Technology Conference (EPTC 2013)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124630550","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Extreme high pressure and high temperature package development","authors":"How Yuan Hwang, Eva Wai Leong Ching, C. Sing, V. Chidambaram, Lee Jong Bum, E. Rong, Gan Chee Lip, Daniel Rhee Min Woo","doi":"10.1109/EPTC.2013.6745746","DOIUrl":"https://doi.org/10.1109/EPTC.2013.6745746","url":null,"abstract":"As oil and gas industries ventured further and deeper into the earth or ocean in search for new reservoirs, the requirements of depth, pressure and temperature are ever expanding. Conventionally, ceramic based hermetic sealed packaging is used for high temperature endurable package. However, for the case of highly pressurized application, the stress on the package is substantial and the hermetically sealed ceramic package cannot survive under a high pressure up to 30kpsi. To overcome this limitation, the authors are proposing to fill high temperature and high pressure endurable protective materials inside of ceramic substrate cavity to absorb the package internal stress caused by the external high pressure loading. The reliability of the package has been successfully demonstrated under combined 30kpsi isostatic pressure and 300°C temperature (HPHT) aging condition for 500 hours as well as thermal cycling condition for 500 cycles.","PeriodicalId":210691,"journal":{"name":"2013 IEEE 15th Electronics Packaging Technology Conference (EPTC 2013)","volume":"85 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130571692","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Systematic modeling of on-chip power grids with decaps in TSV-based 3D chip integration","authors":"Z. Oo","doi":"10.1109/EPTC.2013.6745785","DOIUrl":"https://doi.org/10.1109/EPTC.2013.6745785","url":null,"abstract":"Efficient modeling of power supply noises is crucial for a robust power supply design, especially with increase in the size of on-chip power grids due to emerging 3D chip integration technology. As the power grid is interconnected vertically by through-silicon vias (TSVs), operational currents required by each functional device in integrated circuits (ICs) are supplied through vertical power and ground TSVs, and horizontal power grids. Fast switching speed of the devices become complicated the accurate analysis of the worst case power supply noises. In this paper, a systematic modeling of on-chip power grids with decoupling capacitors - VNCAPs - used in TSV-based chip integration technology is presented using novel equivalent decap circuit model. The equivalent circuit model will be numerically validated and integrated into an efficient modeling for impedance profile of on-chip power grids and analysis of power supply noises in TSV-based 3D chip integration technology.","PeriodicalId":210691,"journal":{"name":"2013 IEEE 15th Electronics Packaging Technology Conference (EPTC 2013)","volume":"55 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120920370","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Size and geometry effects on microstructural evolution in Sn microbumps during isothermal aging","authors":"Hua Xiong, Zhiheng Huang, P. Conway","doi":"10.1109/EPTC.2013.6745764","DOIUrl":"https://doi.org/10.1109/EPTC.2013.6745764","url":null,"abstract":"A phase field model on the Sn-Cu binary reaction is used to systematically study the effects from the size, geometry and stress on the microstructural evolution in Sn microbumps with Cu pads during aging at 150°C. It is found that a thicker interfacial Cu₃Sn layer, a thinner interfacial Cu₆Sn₅ layer and a faster consumption rate of the Cu pad can be obtained by increasing the pad size of the microbump, no matter whether the bulk Cu₆Sn₅ is considered or not. In addition, there are more bulk Cu₆Sn₅ Particles remained by increasing the bump height or by adopting an hourglass-shaped microbump with the latter resulting in a faster consumption of the Cu pads. Furthermore, the amount of the interfacial Cu₆Sn₅ and Cu₃Sn phases is found to be controllable by applying external mechanical loads. A compressive load is in favor of the growth of the interfacial Cu₃Sn phase, while a tensile load can enhance the growth of the interfacial Cu₆Sn₅ phase.","PeriodicalId":210691,"journal":{"name":"2013 IEEE 15th Electronics Packaging Technology Conference (EPTC 2013)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126899510","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Assessment of refinishing processes for electronic components in high reliability applications","authors":"C. Bailey, S. Stoyanov, C. Best, C. Yin, M. Alam, P. Tollafield, P. Stewart, J. Roulston","doi":"10.1109/EPTC.2013.6745704","DOIUrl":"https://doi.org/10.1109/EPTC.2013.6745704","url":null,"abstract":"Refinishing of electronics components, also known as hot solder dip (HSD), is sequence of process steps used to remove original solder alloy coatings from package terminations and replacing the finishes with different type of solder composition. Typically this transformation is from lead-free to eutectic tin-lead solder and aims primarily at mitigating the risk of tin whiskers induced failures. Hot solder dip process is the only practical solution for Aerospace, Defence and High Performance (ADHP) industries which are exempt from lead-free legislations and therefore can adopt this post-manufacturing practice as a strategy for making commercial-of-the-shelf (COTS) components usable in electronics assemblies with high reliability and critical safety requirements. Hot solder dipping has a thermal impact on processed components. Assessing the thermo-mechanical response of components to the refinishing process and their susceptibility to damage is an issue of critical importance. This paper presents the scope of a comprehensive experimental study that aimed at assessing the impact of the thermal shock induced from double dip hot solder dip process on different component types and reports on the findings in relation to their vulnerability and subsequent long-term reliability.","PeriodicalId":210691,"journal":{"name":"2013 IEEE 15th Electronics Packaging Technology Conference (EPTC 2013)","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125701381","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Managing BGA test socket SI characterization","authors":"Lin Chee-Hoe, Ng Hui-Ying, Wong Wui-Weng","doi":"10.1109/EPTC.2013.6745788","DOIUrl":"https://doi.org/10.1109/EPTC.2013.6745788","url":null,"abstract":"In the area of high speed BGA products, such as APUs and GPUs, new revision of NPI (New Product Introduction) comes rapidly, and frequently involves change in package footprint. Test socket for the BGA package has to be characterized every time it involves a socket pin design change. This paper introduces an effective Signal Integrity (SI) characterization method for BGA test sockets used in high speed system level testing platforms. This method is referred as Coupling Pin Extraction Method (CPEM), in this paper. Loop Inductance (Lloop) and Coupling Capacitance (Ccouple) of socket pins under test are critical electromagnetic parameters which can be extracted using the proposed CPEM. CPEM is carefully crafted such that the Lloop and Ccouple can be consistently extracted using both measurement and simulation, with a single package footprint. Well-established 2-port VNA measurement is used in CPEM measurement of the targeted pin to the surrounding pins in a well defined Signal and Ground pin patterns. Similarly, Quasi-static Electromagnetic (Q-EM) simulation can be used to extract that Lloop and Ccouple as mentioned in the above. The extracted Lloop and Ccouple can then be used to derive Characteristic Impedance (Zo), Propagation Delay (Tdelay) and Coupling Coefficient (Kc). These derived parameters are more robust and better to address the SI performance of a high speed BGA socket.","PeriodicalId":210691,"journal":{"name":"2013 IEEE 15th Electronics Packaging Technology Conference (EPTC 2013)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125452455","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Polymeric packaging of high power semiconductor devices: Material selection & reliability assessment","authors":"N. Nobeen, K. Ahmad, D. Whalley, D. Hutt, B. Haworth","doi":"10.1109/EPTC.2013.6745696","DOIUrl":"https://doi.org/10.1109/EPTC.2013.6745696","url":null,"abstract":"For power thyristor devices used in high voltage direct current (HVDC) schemes, hermetic packages are still being used despite plastic packaging having made successful progress towards replacing them in various high reliability applications, e.g. aerospace and military. Although hermetic technologies have demonstrated an excellent history of reliability and performance, they offer several drawbacks, if used for the thyristor devices intended for future HVDC transmission schemes. This is because future HVDC schemes will be required to have higher current/voltage ratings e.g. to meet the increasing energy demands from large and rapidly developing countries, such as China, Brazil, India, etc., and such systems will require thyristors based on larger semiconductor wafer diameters. Consequently, this will drive the packages to be bigger, more fragile and expensive. It is expected that by switching from the present ceramic housings to a polymer material, the device will be more robust, cheaper and lighter than the current hermetic configuration. However, such a shift also provides many challenges in terms of materials selection, design and manufacturing. Potential issues include polymer permeability to moisture, delamination, voiding, crack formation which could all lead to thyristor failure. To assess whether the performance and reliability of a polymer housing can be comparable to current ceramic packages, a polymeric package demonstrator was developed and tested. Along with electrical and thermal modelling studies performed to study the package behaviour, different activities, such as identifying appropriate material candidates and design concepts for the housing, and reliability of the manufactured polymer housing, were also carried out to develop the housing. It is these activities that are discussed in this paper. For instance, from the material selection study, polymers, such as polyimide (PI) and epoxy, were identified as being ideal candidates for the high operating temperature and good electrical performance required from the housing. From the reliability study which comprised of temperature cycling accelerated life tests, the manufactured polymer housing was concluded to be reliable.","PeriodicalId":210691,"journal":{"name":"2013 IEEE 15th Electronics Packaging Technology Conference (EPTC 2013)","volume":"107 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121394205","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Direct eutectic AuSn solder bumping on Al bond pad surface using laser solder ball jetting","authors":"M. Ding, J. Aw, L. Lim, L. Wai, V. S. Rao","doi":"10.1109/EPTC.2013.6745717","DOIUrl":"https://doi.org/10.1109/EPTC.2013.6745717","url":null,"abstract":"Au-rich eutectic AuSn (Au80wt%-Sn20wt%) solder ball alloy is extensively used in MEMS and optoelectronics packaging, for providing flip-chip solder bump interconnections. In this paper, we will look into the possibility of using laser solder ball jetting process for direct eutectic AuSn solder bumping on Al bond pad surface, and compare with eutectic AuSn solder bumping on Al bond pad with Ti/Ni/Au UBM structure. The laser jetted eutectic AuSn solder bumps were observed to wet and form hemi-spherical bumps on the Al bond pad surface, with and without UBM structure. FIB-EDX analysis of the laser jetted eutectic AuSn solder bump on Al bond pad with UBM structure showed formation of dense islands of Au5Sn IMC layer from the top Au finishing layer of the UBM structure. On the other hand, only a few clusters of Au5Sn IMC were formed near to the solder joint of the laser jetted eutectic AuSn solder bump on Al bond pad surface. Ball shear test on the laser jetted eutectic AuSn solder bumps exhibited average solder shear strength of 4.52g/mil2 and 14.22g/mil2, on Al bond pad surface and Al bond pad with UBM structure respectively. Laser jetted eutectic AuSn solder bumps on Al bond pad surface displayed pad lift failure mode, as compared to failure at Al bond pad layer for Al bond pad with UBM structure. In conclusion, eutectic AuSn solder balls could be bumped onto Al bond pad surface via laser jetting.","PeriodicalId":210691,"journal":{"name":"2013 IEEE 15th Electronics Packaging Technology Conference (EPTC 2013)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133757257","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}