2013 IEEE 15th Electronics Packaging Technology Conference (EPTC 2013)最新文献

{"title":"Thermal characterization and simulation study of 2.5D packages with multi-chip module on through silicon interposer","authors":"H. Zhang, X. Zhang, B. L. Lau, S. Lim, L. Ding, M. B. Yu, Y. J. Lee","doi":"10.1109/EPTC.2013.6745743","DOIUrl":"https://doi.org/10.1109/EPTC.2013.6745743","url":null,"abstract":"Next generation of heterogeneous integration requires 2.5D package on interposer as enabling technology for less signal delay, faster speed, and more functionality. In this work, thermal characterization and simulation of a 2.5D package with multi chips on through silicon interposer (TSI) are reported. Two dummy chips with chip sizes of 7.6×10.9mm and 8mm×8mm, respectively, are arranged on the interposer through the flip chip bumping and joining process. To facilitate the thermal characterization, a thermal test chip of 5.08×5.08mm is embedded on the same interposer for thermal test and simulation validation. In either molded or bare die BGA package format, the thermal test vehicles are brought for thermal characterization, including Theta JA Theta JB measurement conforming with the JEDEC standards. It is found that the overmolded package has slightly lower thermal resistances than the bare die package. In addition, the Theta JC, namely, the thermal resistance from the junction to the top casing is also characterized through a high performance cold plate. Besides the thermal measurements, thermal simulation models under different boundary conditions are established, respectively, to compare with the thermal measurements. Good agreements are generally achieved between simulation and measurements. Further simulation is also conducted to study the effects of overmold thickness and power dissipation from the multi chips module on the interposer.","PeriodicalId":210691,"journal":{"name":"2013 IEEE 15th Electronics Packaging Technology Conference (EPTC 2013)","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116595153","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Fabrication of low cost spherical alkali atom vapor cells by combining a low temperature anodic bonding and a Chemical Foaming Process (CFP)","authors":"Youpeng Chen, J. Shang, Yu Ji","doi":"10.1109/EPTC.2013.6745833","DOIUrl":"https://doi.org/10.1109/EPTC.2013.6745833","url":null,"abstract":"In this presentation, a novel fabrication process, based on our previous research [4-5], used to manufacture spherical alkali atom vapor cells for miniaturized atomic clock application will be presented, allowing low-cost wafer level batch fabrication and assembly. This method combines low temperature anodic bonding technique and Chemical Foaming Process (CFP) for producing spherical alkali atom vapor cells. The Rb (Rubidium) vapor cell, which consists of two cavities, has been carefully designed. The smaller one which taken as reaction chamber connected to the larger one which served as a working chamber with micro-channel can prevent reactant from entering into working chamber improves the purity of Rb in the working chamber. The fabrication is based on UV laser equipment, and then a thin Pyrex7740 glass wafer is anodic bonded to the patterned silicon wafer. Subsequently, the bonded wafer is heated over the softening point of the glass (Tg=821°C) and hydrogen gas released by TiH2 blowing the glass into spherical shells. During this process the reaction take place and produce rubidium vapor which through microchannel to enter working chamber. The Rb vapor cell is characterized by EDS (Energy Dispersive Spectroscopy) and ultraviolet spectrophotometer. Results show that during fabrication process the rubidium produced and Rb vapor cell is fabricated successfully.","PeriodicalId":210691,"journal":{"name":"2013 IEEE 15th Electronics Packaging Technology Conference (EPTC 2013)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126096679","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Study on thermo-mechanical reliability of 3D stacked chip SiP based on cavity substrate","authors":"Fengze Hou, Jun Li, Huiqin Xie, Xueping Guo, Liqiang Cao, Yuan Lu, L. Wan","doi":"10.1109/EPTC.2013.6745848","DOIUrl":"https://doi.org/10.1109/EPTC.2013.6745848","url":null,"abstract":"In this paper, a novel 3D stacked chip SiP structure based on cavity substrate is proposed. For the structure of cavity substrate is asymmetric, the thermo-mechanical reliability issues of the 3D SiP structure are very important and necessary to be studied. When molding compound is injected into the 3D SiP structure, it contacts with other parts of the structure. Because Young's modulus of the molding compound varies with temperature during cooling process from molding temperature to room temperature and CTEs of different materials are mismatched, the effect of molding compound cooling process on the reliability of 3D SiP is necessary to be investigated. The thermo-mechanical reliability FEM simulation of the molding compound cooling process from molding temperature 125 °C to room temperature 25 °C is performed to study the warpage issue of the 3D package SiP. In order to conduct the molding compound cooling simulation correctly, Young's modulus of molding compound dependent on time and temperature is tested by using DMA. The simulation result shows that the deformation won't bring the warpage for the 3D SiP. Besides, the thermo-mechanical reliability FEM simulation of the 3D package module under thermal cycling (-40/125 °C) is evaluated to find out the stress and strain distribution of the 3D package module, the BGA and to predict the warpage, delamination, die cracking, solder joint cracking, excessive substrate deformation and cracking of the 3D package module. The simulation results indicate that the 3D package module has higher thermo-mechanical reliability.","PeriodicalId":210691,"journal":{"name":"2013 IEEE 15th Electronics Packaging Technology Conference (EPTC 2013)","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127296696","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Process integration of solder bumps and Cu pillar microbumps on 2.5D fine pitch TSV interposer","authors":"S. L. Pei-Siang, L. Ding, Mingbin Yu, M. Ding, Sorono Dexter Velez, V. S. Rao","doi":"10.1109/EPTC.2013.6745756","DOIUrl":"https://doi.org/10.1109/EPTC.2013.6745756","url":null,"abstract":"The use of portable electronic devices like smart phones and tablets results in high demand for more function, smaller dimensions and reduced power consumption requirements. To meet these challenges, electronic package design uses thinner chips with fine pitch bumping. There has been active development in 2.5D and 3D IC packages with through silicon via (TSV). Tighter interconnection in addition to the increased density in the circuit in 2.5D and 3D IC systems provide higher performance with lower power consumption [1]. In addition, the down scaling trend of CMOS technology beyond 28nm node requires smaller chip size for a given input/output (I/O) count, pushing the interconnect pitch smaller and smaller. When the bump pitch is less than 50μm and the gap between the die and substrate is lesser than 25μm, traditional capillary underfill (CUF) material is likely to require a vacuum or pressure assisted process to pull the underfill and fill the gaps without any voids [2]. The narrower gap also makes flux cleaning after reflow more challenging. The development of wafer-level underfills can bring the financial benefits of wafer-level processing to flip chip assembly and packaging. The flip chip assembly is the application of underfill at the wafer level, eliminating the dispense, flow, and separate cure steps associated with assemblies utilizing capillary-flow underfills. In addition, the wafer-level material should include fluxing capabilities similar to no-flow underfills [3]. In this paper we describe the assembly process and challenges of the 100μm thin 2.5D TSV Si interposer to the test substrate and the assembly of three different test chips onto TSV Si interposer using capillary underfill and WL-UF (NST series from Nissan Chemical Industries, Ltd). The TSV Si interposer provides high density multilevel routing on the frontside of the wafers and through-silicon vias (TSVs) to connect the frontside metallization with the backside metallization for connection to the PCB [4].","PeriodicalId":210691,"journal":{"name":"2013 IEEE 15th Electronics Packaging Technology Conference (EPTC 2013)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129152970","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Chip Package Interaction(CPI) risk assessment on 28nm Back End of Line(BEOL) stack of a large I/O chip using compact 3D FEA modeling","authors":"Chirag Shah, F. Mirza, C. Premachandran","doi":"10.1109/EPTC.2013.6745691","DOIUrl":"https://doi.org/10.1109/EPTC.2013.6745691","url":null,"abstract":"Chip Package Interaction (CPI) is a widely recognized quality and reliability challenge for flip-chip packages due to the ultra low-K materials used within the silicon Back End of Line (BEOL). This paper discusses a predictive finite element model developed to address this challenge. Furthermore, for advanced flip-chip package models, it is challenging to have the entire C4 bump array within the model due to the extremely large pin count (I/O) fitted at a fine pitch within a large die. As an example, for CPU chips, it is not uncommon to have chip contain over 10,000 C4 bumps. Accounting for such large bump count with FEA models, makes the analyses not just computationally expensive but also often impossible. The proposed study will try to address these challenges by demonstrating a “compact” 3D modeling approach for 28nm chip stack. The effective properties developed for C4 joints will also be adjusted to account for Cu pillar joints. Lastly, the model has been validated with full bump array models that do not use effective properties to confirm the usefulness and scalability of this approach.","PeriodicalId":210691,"journal":{"name":"2013 IEEE 15th Electronics Packaging Technology Conference (EPTC 2013)","volume":"62 12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123302622","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Effects of metallic nanoparticle doped flux on interfacial intermetallic compounds between Sn-3.0Ag-0.5Cu and copper substrate","authors":"S. Ghosh, A. Haseeb, A. Afifi","doi":"10.1109/EPTC.2013.6745676","DOIUrl":"https://doi.org/10.1109/EPTC.2013.6745676","url":null,"abstract":"Intermetallic compounds (IMCs) formed between solder and substrate play a vital role in determining the long term reliability of microelectronic packages. Various attempts have been made by the researchers to control the morphology and thickness of IMC layers. The aim of this study is to investigate the effects of nanoparticle dopants into flux on the morphology and thickness of interfacial intermetallic compounds layers. Different types of nano-sized metallic particles were studied to understand their effects on the wetting characteristics and interfacial microstructural evaluations after first reflow by adding nanoparticles to flux at various percentages. Nanoparticles were dispersed manually with a water soluble flux to prepare a nanoparticles doped flux which was placed on the copper substrate. Lead-free Sn-3.0Ag-0.5Cu (SAC 305) solder balls of diameter 0.45mm were then placed on top of the flux and were reflowed in a reflow oven at a peak temperature of 240°C for 45s. Wetting area, contact angle and interfacial microstructure were investigated by optical microscopy, scanning electron microscopy (SEM), field emission scanning electron microscopy (FESEM) and energy-dispersive x-ray spectroscopy (EDX). It was found that doping of cobalt (Co) and nickel (Ni) nanoparticles with flux was successful in incorporating Co and Ni into the solder joint. Microstructural observations showed that both Co and Ni nanoparticles changed the interfacial morphology from a scallop to a planer type. This was suggested to be caused by alloying effect of these elements. In case of Co, this morphological change was evident down to 0.25 wt% Co addition to flux. For Ni, this effect was notable even at 0.1 wt% Ni addition to flux. Therefore, Nano doping of flux can be successfully used to cause in situ targeted alloying at the solder/substrate interface.","PeriodicalId":210691,"journal":{"name":"2013 IEEE 15th Electronics Packaging Technology Conference (EPTC 2013)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123145855","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Thermal-mechanical considerations of a novel power module with high junction temperature","authors":"H. Ling, Lee Yong Jiun, How Yuan Hwang, Z. Yun, D. Rhee","doi":"10.1109/EPTC.2013.6745770","DOIUrl":"https://doi.org/10.1109/EPTC.2013.6745770","url":null,"abstract":"Mechanical and thermal analyses are performed for a power module with target junction temperature of 220°C. The initial design of the package consists of six silicon carbide dies with electrical connections traditionally made by wires being replaced by copper clips and flip chip joints. From mechanical simulations, it is found that compliance of the copper clips affect the stress level at the attachment layer. Several clip designs were investigated and results shows that the design with the greatest flexibility will result in the lowest stress at the attachment layer. For properties of the molding compound, the higher the coefficient of thermal expansion (CTE), the larger the attachment stress whereas for molding compound modulus, the attachment stress can increase or decrease, depending on the corresponding CTE. From thermal simulations, it is found that voids at the attachment layer marginally affect the thermal characteristics while thickness and properties of the thermal interface materials (TIM) greatly affect the thermal performance. The findings suggest that when a metallic attachment material is chosen, dimensional parameters and material choices of the attachment material is less critical to the thermal performance. From power cycling analyses, it is observed that the rise in temperature is largely concentrated around the dies which are powered-up.","PeriodicalId":210691,"journal":{"name":"2013 IEEE 15th Electronics Packaging Technology Conference (EPTC 2013)","volume":"256 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115838495","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"X-parameter techniques for signal integrity in high-speed links","authors":"J. Schutt-Ainé, T. Comberiate","doi":"10.1109/EPTC.2013.6745719","DOIUrl":"https://doi.org/10.1109/EPTC.2013.6745719","url":null,"abstract":"X-parameters have been shown to have a wide array of applications in the modeling of nonlinear devices and systems. In this work we demonstrate that they can be combined with LIM and IBIS to produce robust models for high-speed links. In particular IBIS data generation from X parameters is demonstrated and its advantage over currently available methods is discussed.","PeriodicalId":210691,"journal":{"name":"2013 IEEE 15th Electronics Packaging Technology Conference (EPTC 2013)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130678132","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Study on dynamic modeling and reliability analysis of wafer thinning process for TSV wafer","authors":"F. Che, W. Lee, Xiaowu Zhang","doi":"10.1109/EPTC.2013.6745823","DOIUrl":"https://doi.org/10.1109/EPTC.2013.6745823","url":null,"abstract":"Through-silicon-via (TSV) technology permits devices to be placed and wired in the third dimension. Currently, there is a strong motivation for the semiconductor industry to move to 3D integration using the TSV approach due to many advantages of TSV application. However, there are also some challenges for TSV processes. One of the challenges is TSV wafer thinning process. In this paper, a dynamic finite element modeling methodology was established and used to investigate the TSV process induced wafer stress. It was found that wafer surface roughness, TSV wafer thickness, bonding/debonding material, TSV feature size have impact on TSV wafer stress under the TSV wafer thinning process.","PeriodicalId":210691,"journal":{"name":"2013 IEEE 15th Electronics Packaging Technology Conference (EPTC 2013)","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126921556","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Thermal performance of a double-action pulsed jet CPU cooler","authors":"T. Chandratilleke, Dibakar Rakshit","doi":"10.1109/EPTC.2013.6745741","DOIUrl":"https://doi.org/10.1109/EPTC.2013.6745741","url":null,"abstract":"More efficient and compact thermal management techniques are critical for the development of Central Processing Units (CPU) embedded in complex and powerful modern computer systems. Introducing a technological alternative to conventional fan-cooled systems, this paper presents an experimental investigation of a double-action CPU cooler based on the pulsed (or synthetic) jet principle. The study develops a prototype of this new CPU cooler and tests it for a range of operating conditions to ascertain its cooling capabilities. The performance of this device is compared with a conventional fan CPU heat sink design for evaluating the relative thermal advantages of the new configuration. It is observed that the pulsed-jet CPU cooler achieves about 1.5 times more heat removal rate than a comparable fan CPU cooler. Whilst thermal optimisation is feasible, it is recognised that this pulsed jet arrangement has unique surface cooling ability without additional fluid circuits, making it particularly desirable for high-capacity electronic cooling applications.","PeriodicalId":210691,"journal":{"name":"2013 IEEE 15th Electronics Packaging Technology Conference (EPTC 2013)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116928344","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}