Chip Package Interaction(CPI) risk assessment on 28nm Back End of Line(BEOL) stack of a large I/O chip using compact 3D FEA modeling

Abstract

Chip Package Interaction (CPI) is a widely recognized quality and reliability challenge for flip-chip packages due to the ultra low-K materials used within the silicon Back End of Line (BEOL). This paper discusses a predictive finite element model developed to address this challenge. Furthermore, for advanced flip-chip package models, it is challenging to have the entire C4 bump array within the model due to the extremely large pin count (I/O) fitted at a fine pitch within a large die. As an example, for CPU chips, it is not uncommon to have chip contain over 10,000 C4 bumps. Accounting for such large bump count with FEA models, makes the analyses not just computationally expensive but also often impossible. The proposed study will try to address these challenges by demonstrating a “compact” 3D modeling approach for 28nm chip stack. The effective properties developed for C4 joints will also be adjusted to account for Cu pillar joints. Lastly, the model has been validated with full bump array models that do not use effective properties to confirm the usefulness and scalability of this approach.