2013 IEEE 15th Electronics Packaging Technology Conference (EPTC 2013)最新文献

{"title":"Graphene based heat spreader for high power chip cooling using flip-chip technology","authors":"Shirong Huang, Yong Zhang, Shuangxi Sun, Xiaogang Fan, Ling Wang, Yifeng Fu, Yan Zhang, Johan Liu","doi":"10.1109/EPTC.2013.6745740","DOIUrl":"https://doi.org/10.1109/EPTC.2013.6745740","url":null,"abstract":"Monolayer graphene was synthesized through thermal chemical vapor deposition (TCVD) as heat spreader for chip cooling. Platinum (Pt) serpentine functioned as hot spot on the thermal testing chip. The thermal testing chip with monolayer graphene film attached was bonded using flip-chip technology. The temperature at the hot spot with a monolayer graphene film as heat spreader was decreased by about 12°C and had a more uniform temperature compared to those without graphene heat spreader when driven by a heat flux of about 640W/cm2. Further improvements to the cooling performance of graphene heat spreader could be made by optimizing the synthesis parameters and transfer process of graphene films.","PeriodicalId":210691,"journal":{"name":"2013 IEEE 15th Electronics Packaging Technology Conference (EPTC 2013)","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130398651","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Non-linear deflection analysis of pin-on-package testing using FEA","authors":"N. Subramanian, Koo Kok Kiat, Tye Ching Yun","doi":"10.1109/EPTC.2013.6745753","DOIUrl":"https://doi.org/10.1109/EPTC.2013.6745753","url":null,"abstract":"Integrated circuit packages are tested for component function before shipped to customers. The testing involves probing of the package leads with Pogo pins/spring probes having sharp-edge tips manufactured from harder BeCu or Pd alloys. The spring-controlled pins forced onto the pad surface penetrate the surface oxide layers to establish electrical contact with the metal underneath for assessment of test parameters. However, this also can lead to form scratch marks and pad cracks on the lead surfaces and achieving good contact with minimum damage to pad surfaces is important. Also pin tips tend to deform due to mechanical interactions with the package lead & wear upon continuous insertions. Since reliability testing over millions of insertions can be a very time consuming process, here's, an attempt to utilise simulation method/approach to quantify plunger pin insertion induced stress/strain at the pin-pad interfaces & evaluate variations in tip profile on probe and pad performance in a standard manner. This paper describes a non-linear contact analysis of spring-loaded palladium vertical probes with wedge & crown tip profiles insertion onto lead surface during package testing and evaluating penetration induced deformation, stress and strain at contacting interfaces of both probe tip and pad and compared with indentation measurements. The non-linear analysis involves Bilinear Isotropic hardening plasticity (BISO) elasto-plastic material and rough contacts in Ansys Workbench environment.","PeriodicalId":210691,"journal":{"name":"2013 IEEE 15th Electronics Packaging Technology Conference (EPTC 2013)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130599322","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Lead frame fanning and broken connecting bars elimination through design change and molding optimization","authors":"L. Lim, T. Li","doi":"10.1109/EPTC.2013.6745712","DOIUrl":"https://doi.org/10.1109/EPTC.2013.6745712","url":null,"abstract":"Designing of a leadless package is very challenging as there are many manufacturability considerations that need to be considered prior to designing the lead frame. The concerns are lead frame warpage, high sawing burr, lead frame delamination due to insufficient mold locking and etc. During the development of a dual leadless package of 7mm×7mm, these concerns were being addressed by design features such as half etched connecting bars to reduce copper loading during package sawing, additional stress relief slots and mold locking holes. Dummy leads were also designed in to balance the copper material on both sides of the connecting bars as the package design has a non symmetry land pattern. However due to the complicated lead and DAP design structure that restrict the mold compound flow, higher molding pressure is required in order to avoid any incomplete filling. This high transfer pressure eventually caused fanning of connecting bars and broken tie bars which also caused offset cutting and high saw burr. In this paper, we studied on how the combination of lead frame design, molding process optimization and package sawing process improvement could help to resolve the issue. This was done by lead frame warpage simulation and design of experiment on molding parameters and design of experiment on sawing process parameter and type of blade used.","PeriodicalId":210691,"journal":{"name":"2013 IEEE 15th Electronics Packaging Technology Conference (EPTC 2013)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121090697","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Mitigation of mechanical fracture of polycrystalline silicon structure in MEMS capacitive microphones","authors":"Tang Kum Cheong, Cheam Daw Don","doi":"10.1109/EPTC.2013.6745820","DOIUrl":"https://doi.org/10.1109/EPTC.2013.6745820","url":null,"abstract":"Micro-machined capacitive microphones, currently well sought-after owing to increasing proliferation of handheld electronic devices, contain two parallel diaphragms that are made of thin-film polycrystalline silicon (polysilicon) - a relatively brittle material. Without sound process and fabrication controls, undesirable repercussions such as elevated production costs and unacceptable device yield levels may occur. This paper describes our experience in the microfabrication of capacitive microphones and proposed solution to minimize the risks of thin polysilicon diaphragms mechanical failure. We found the unintended presence of buried oxide keyholes beneath a polysilicon layer as the leading cause of thin-film rupture when the substrate was processed at elevated temperatures as part of downstream process procedures. We believe the keyholes were formed as a result of the “bread-loafing” effect and the reduction in keyhole size was verified as a contributing factor to minimizing the possibility of material rupture, which leads to better device yield.","PeriodicalId":210691,"journal":{"name":"2013 IEEE 15th Electronics Packaging Technology Conference (EPTC 2013)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128885582","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"High performance integrated passive devices (ipds) on low cost through silicon interposer (LC-TSI)","authors":"Cheng Jin, Boyu Zheng, L. Ding, Rui Li, K. Chang","doi":"10.1109/EPTC.2013.6745840","DOIUrl":"https://doi.org/10.1109/EPTC.2013.6745840","url":null,"abstract":"This paper presents the design, fabrication and characterization of integrated passive devices (IPDs) on low cost through silicon interposer (LC-TSI). The performance of symmetrical spiral inductors is presented and analyzed in this paper. The effect of space between traces and the width of the trace on the Q-factor are studied. In addition, the inductors with TSV around and under are also discussed. On the TSI platform, some radio-frequency (RF) IPDs are also designed, including a millimeter-wave (mmWave) antenna working at 77 GHz for the automotive radar application. A bandpass filter based on the quarter-mode substrate integrated waveguide (QMSIW) is also designed on the TSI platform. The performance of these structures is given and the results show that the TSI platform is an attractive and promising method as a carrier to design IPDs and RF-IPD working at high frequency.","PeriodicalId":210691,"journal":{"name":"2013 IEEE 15th Electronics Packaging Technology Conference (EPTC 2013)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130649122","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Chip to chip hermetic bonding and multi-chip stacking using CuSn bonding technology","authors":"V. N. Sekhar, L. J. Su, Justin Wai Hong., Chen Bangtao","doi":"10.1109/EPTC.2013.6745699","DOIUrl":"https://doi.org/10.1109/EPTC.2013.6745699","url":null,"abstract":"In this study, heterogeneous multi-chip stacking with three chips has been demonstrated for 100 μm thin chips using CuSn bonding. Two different die sizes 12×12mm and 3×3mm have been considered and studied. The width of bonding seal rings is 100 μm. For a hermeticity test, cavity chips were bonded to obtain the proper cavity volume of helium leak test as per MIL-STD 883E. The cavity chip size is identical with full wafer thickness and the cavities dimension as 10 mm × 10 mm × 200 μm. In order to stack three dies, CuSn seal rings were patterned onto the front and bottom side of 8” wafers. After patterning CuSn seal rings, the device wafers were temporarily bonded onto carrier wafers as flipped over, and then wafer thinning to 100μm thickness was done. Alignment bonding has been carried out during temporary bonding process. The identical seal ring patterns were processed onto the thinned device wafers. After backside processing of device wafers, thermal slide-off de-bonding method has been employed for de-bonding. The double side patterned wafers were successfully de-bonded for the wafer thicknesses of 100 μm. Cavity chip wafers were fabricated by using Si DRIE process.","PeriodicalId":210691,"journal":{"name":"2013 IEEE 15th Electronics Packaging Technology Conference (EPTC 2013)","volume":"74 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133867773","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Environmental ageing effects on the electrical resistance of silver-epoxy electrically conductive adhesive joints to a molybdenum electrode","authors":"V. Ivanov, K. Wolter","doi":"10.1109/EPTC.2013.6745681","DOIUrl":"https://doi.org/10.1109/EPTC.2013.6745681","url":null,"abstract":"The electrically conductive adhesives (ECAs) provide a large amount of opportunities for the electronic manufacturing. They have much lower processing temperatures, so the heat impact on the electronic components can be reduced. It makes them suitable for interconnecting the temperature sensitive elements in the devices, for example in liquid-crystal displays or modules of flexible thin film solar cells. However, this type of interconnections has to overcome some challenges. As the contact to noble metals has relatively low electrical resistance and is stable to the environment loads, in the ECA joints to non-noble metals the degradation happens (increase of contact resistance, decrease of adhesion). That's why it is important to investigate such type of joints for stability under different ageing conditions. Most of the latest investigations in this field are concentrated on the ECA joints to Sn, because this non-noble metal is widely used in the electronic packaging. This system of contacted materials remains stable under the (120°C) thermal ageing, but suffer from increase of the contact resistance after heat/humidity ageing (85 °C/85% relative humidity) and accelerated thermal cycling (-40 to 125°C). Another contact of non-noble metal to ECA that needs to be investigated is Mo to ECA. Molybdenum is used as a back contact in thin film solar cell manufacturing and the ECAs are used for interconnection and assembling the individual cells in modules. The focus of this work is to investigate the contact behavior between ECAs and non-noble, molybdenum films under different ageing conditions. The experiments are focused on the electrical conductivity. The goal of the work is to investigate the degradation behavior of non-noble metal - ECA joints and to predict the reliability of this type of an electrical contact.","PeriodicalId":210691,"journal":{"name":"2013 IEEE 15th Electronics Packaging Technology Conference (EPTC 2013)","volume":"223 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133511081","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Developments in 2.5D: The role of silicon interposers","authors":"T. Lenihan, L. Matthew, E. J. Vardaman","doi":"10.1109/EPTC.2013.6745683","DOIUrl":"https://doi.org/10.1109/EPTC.2013.6745683","url":null,"abstract":"Silicon interposers are a technology with a history of multiple incarnations over more than 20 years. Today, interposers with TSVs are considered an alternative to 3D IC structures where die are stacked on top of each other using TSVs. Applications for interposers with TSVs include ASICs for networking applications and FPGAs. Xilinx's Virtex-7 2000T FPGA was one of the first new products using a silicon interposer with TSVs for a partitioned IC design. Co-design with new packaging technology has resulted in a new FPGA that allows reduced system cost and increased performance with lower power. By not having to drive off-chip I/Os across PCB traces to adjacent FPGAs, high-performance applications that have previously used multiple FPGAs can be replaced with a single package solution that provides high-bandwidth, low-latency, power-efficient interconnect between the FPGA die. The key to the performance gains is the partitioning of an FPGA die into four “slices” that are mounted on a silicon interposer. Is this a unique application or are there other potential applications for interposers in applications with GPUs or ASICs? Today's interposers are passive structures, but there are potential for the use of integrated passives in the interposer. How do these applications differ from the technology introduced in previous generations? This presentation highlights the new drivers for the introduction of silicon interposers. The presentation also examines the latest developments in the infrastructure to support the development of this technology, including suppliers. The article also highlights the differences between adoption of today's interposers and the thin-film on silicon (MCM-D) of the past.","PeriodicalId":210691,"journal":{"name":"2013 IEEE 15th Electronics Packaging Technology Conference (EPTC 2013)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133603795","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Investigating the temperature effect of reliability on integration IC 3D packaging under drop test","authors":"Hao Chen, Yi-Che Chiang, T. Hung, K. Chiang","doi":"10.1109/EPTC.2013.6745773","DOIUrl":"https://doi.org/10.1109/EPTC.2013.6745773","url":null,"abstract":"Technological developments and increasing user demand have driven the evolution of electronic packaging from traditional single-chip packaging to multi-chip packaging, i.e., three-dimensional integrated circuit (3D-IC) packaging. The main advantages of 3D-IC packaging are its small size and lower signal delay. Thus, 3D-IC packaging has been broadly used in mobile electronic devices. Mobile electronic devices are prone to being dropped because of their portability. During drop impact, the temperature inside the packages becomes higher than ambient temperature especially for 3-D packaging, which would influence physical behavior of packaging. A simulation that uses the Input-G method was adopted to analyze the dynamic behavior of electronic packaging. Finite element (FE) model analysis that considers glass transition temperature (Tg) was performed to investigate the effect of temperature. The results showed that the reliability of electronic packaging with underfill might be worse than that without underfill when temperature loading is higher than Tg. This study focuses on drop reliability and considers the effect of Tg. An FE model was established based on a real 3D-IC integration package to predict the drop life by using CoffinManson semi-empirical equation. First, thermal stress analysis would be The drop analysis conducted after the thermal stress analysis indicates that the plastic strain of solder joint increased evidently when considering the effect of temperature during drop analysis and that a temperature higher than Tg has a more obvious influence on strain accumulation during thermal stress analysis than during drop impact analysis. Finally, the drop reliability of 3D-IC was predicted. For a structure without underfill, the drop life can be predicted reasonably, whereas it will be overestimated when the structure has underfill. These different findings may be due to the perfect bonding provided by the underfill during each drop in the simulation, which is unlike actual, real-world situations.","PeriodicalId":210691,"journal":{"name":"2013 IEEE 15th Electronics Packaging Technology Conference (EPTC 2013)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130174653","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Wafer reconstruction: An alternative 3D integration process flow","authors":"Teng Wang, José Luís Silva, R. Daily, G. Capuz, Mario Gonzalez, Kenneth June Rebibis, S. Kroehnert, E. Beyne","doi":"10.1109/EPTC.2013.6745754","DOIUrl":"https://doi.org/10.1109/EPTC.2013.6745754","url":null,"abstract":"Wafer reconstruction is a process of forming an integral handle-able wafer by filling the gaps between the dies after die-to-wafer assembly to allow for further processing on the landing wafer, e.g. thinning, redistribution layer deposition, and bumping. This paper examines key aspects and challenges of different wafer reconstruction process flows. Based on analytical and finite element method modeling, guidelines for material selection and structural design are generated. One selected process flow is successfully demonstrated in a typical 300 mm eWLB production environment, proving the feasibility of wafer reconstruction as a 3D integration process flow.","PeriodicalId":210691,"journal":{"name":"2013 IEEE 15th Electronics Packaging Technology Conference (EPTC 2013)","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133355398","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}