Chip to chip hermetic bonding and multi-chip stacking using CuSn bonding technology

In this study, heterogeneous multi-chip stacking with three chips has been demonstrated for 100 μm thin chips using CuSn bonding. Two different die sizes 12×12mm and 3×3mm have been considered and studied. The width of bonding seal rings is 100 μm. For a hermeticity test, cavity chips were bonded to obtain the proper cavity volume of helium leak test as per MIL-STD 883E. The cavity chip size is identical with full wafer thickness and the cavities dimension as 10 mm × 10 mm × 200 μm. In order to stack three dies, CuSn seal rings were patterned onto the front and bottom side of 8” wafers. After patterning CuSn seal rings, the device wafers were temporarily bonded onto carrier wafers as flipped over, and then wafer thinning to 100μm thickness was done. Alignment bonding has been carried out during temporary bonding process. The identical seal ring patterns were processed onto the thinned device wafers. After backside processing of device wafers, thermal slide-off de-bonding method has been employed for de-bonding. The double side patterned wafers were successfully de-bonded for the wafer thicknesses of 100 μm. Cavity chip wafers were fabricated by using Si DRIE process.